fpga
play

FPGA 4. 4. Design ign o of r rapid id prot otot otype w with - PowerPoint PPT Presentation

Oct 27, 2023 •244 likes •497 views

Overv rvie iew 1. Over 1. erview ew 2. 2. Ab About t HyBu yBus Embedded 1. 1. History ry System 2. 2. Busin Bu siness a s area Application 3. 3. Produ ducts Processor 3. Fea 3. eature o e of Zyn ynq & &

  2. Overv rvie iew 1. Over 1. erview ew 2. 2. Ab About t HyBu yBus Embedded 1. 1. History ry System 2. 2. Busin Bu siness a s area Application 3. 3. Produ ducts Processor 3. Fea 3. eature o e of Zyn ynq & & V210 S Sys ystem 1. 1. Zynq nq-7000 dev device f fea eature 2. 2. Compare V2 V210 wi 10 with Zynq nq FPGA 4. 4. Design ign o of r rapid id prot otot otype w with Zynq ynq XILINX ALTERA 5. 5. Implement nt the des e design u n using ng X Xilinx nx LATTICE dev development nt en environm nment nt Zynq ASIC SoCFPGA 6. 6. Co Conc nclusion 2

  3. About Ab t HyBu Bus : : History  CEO : Mr. Tae Hyung Kim ● Develop HMI(Human Machine Interface) OEM product for LSIS  Establish : Sep. 28. 2001 ● LG Display Mobile LCD in-Line inspection(Long life cycle, pattern) ● Export LCD inspection (china BOE, TIANMA) Current ● Develop Medical Device Embedded System Main Platform  Capital : USD 450,000 (Dental, CT, Patient monitor, aesthetic Lager device) ● Build Ass’y Line (Line, Chamber, ICT machine, ESD)  Sales(volume) : USD 7 Million ● Develop AFC(Automatic Fare Collection) System (Korea subway) ● Partnership with ORACLE for Embedded DB business  Employee : 39 people (21 engineer) ● Participating into intelligent U-City project by Ministry of Land, Transport, and Maritime Affairs  Main Products : ● Develop U-Sensor Network System(based TI CC2430, 2420) - Embedded System Solution ● Certified as INNO-BIZ (Technical Innovation Business Company) ● Certified as ISO14001/ISO9001 by Korean Government - Mobile Display Tester/Jig ● Contract of Embedded Training with Samsung Electronics - Embedded OEM/ODM(HMI) Service ● Contract of Ubiquitous Sensor Network Crossbow Korea Distributor ● Established Ubiquitous Sensor Network Research Institute (in Yonsei Univ.) - Embedded Education Service ● branch HyBustech (at Deagu city) ● Export Embedded Linux Education Kit at 150 Chinese Universities (through Intel China) ● Certified as a Venture Company by Korean Government ● Established HyBus Research Institute ● Distributor Contract in Japan/USA/Taiwan/China/India/Singapore ● Established HyBus Co., Ltd. (Sep. 2001) ● Released Embedded Linux System DK based Intel SA1110 AP ● Released Embedded Linux based MPC850 AP ● Contract of Intelligence Information Terminal Development with ETRI Venture Company INNO-BIZ Research Institute ● Enrolled as a Member of Korea embedded software industry association 3

  4. Ab About t HyBu Bus : : 1. Embedded System Business - Embedded Development Tool - Embedded CPU Design House - Embedded S/W 2. Programmable FPGA System Business - FPGA OEM/ODM - FPGA Design Service - ALTERA Board & Design Partner 3. Customer - Samsung Embedded - LSIS Division Display IoT/Education Division Division 1. Education Consulting & Tool 1. Display PG & Tester - Embedded Linux Education kit 2. Display Panel Inspection - FPGA Education kit 3. Customer 2. IoT Platform - LG Display 3. Customer - Samsung Display - University - TOC, BOE Hydis(china) - Polytechnic college and high school - Education center 4

  5. About Ab t HyBu Bus : : HMI(Human Machin Interface) AFC(Auto Fare Collection) System Intelligent RF-Gate Control Board w/ OS Smart PDU (Power Distribution Unit) Dental X-Ray device Linux system based ARM Embedded FPGA (Image processing Board) Division Patient Monitor Embedded computing board w/ OS Display IoT/Education Flat-Panel Digital Detector Division Gig-E Network board(include OS) Division X-Hyper320TKU X-Smart4412TKU PDK3200 H-FPGA-DIGCOM OLED/LCD Tester & Pattern Generator H-Smart4412T H-RK1 HBT3 : Pattern Generator 5

  6. Ab About t HyBu Bus : : Classification by performance List Low-End Middle-End High-End Core Cortex-M series Cortex-A8 Single core Cortex-A15 Qaud core Atmega128/256 (Arduino Cortex-A9 MPcore Cortex-A5x w/ A7 mixed core UNO/MEGA) OS Firmware, RTOS, Arduino RTOS, Linux, Window, Arduino Linux, Window, Android App Biological Signal processing (ECG, Patient Monitor LCD inspection equipment SpO2, etc) AFC Education equipment Arduino LCD inspection equipment etc IoT HMI Etc Products TI/ST Cortex-M Microcontroller Samsung s5pv210 Nvidia Tegra series Atmel Atmega series Marvell PXA3/2xx series Qualcomm Snapdragon series Freescale i.MX2xx series Freescale i.MX6/7 series 6

  7. Fea eature o e of Zynq ynq & V210 S Sys ystem em * In the Xilinx doc excerpt 7

  8. Fea eature o e of Zynq ynq & V210 S Sys ystem em Compare V210 with Zynq V210 Spec Zynq Spec Compare Cortex-A8 Single core 1GHz Cortex-A9 Single/Dual core up to 1GHz Better - 32/32KB I/D Cache, 512KB L2 Cache - 32/32KB I/D Cache, 512KB L2 Cache Used 3 rd party IP 2D/3D Graphic Accelerator None USB 2.0 OTG USB 2.0 OTG x2 Almost same SD/SDIO/HS-MMC x4 SD/SDIO/HS-MMC x2 Almost same LPDDR1/2, DDR2 LPDDR2/3, DDR2/3 Better NAND/OneNAND/NOR QSPI/NAND/NOR Almost same 10CH 12bit ADC 17CH 12bit ADC x2 Better None 1Gbit Ethernet Better Used 3 rd party IP MIPI-DSI/CSI None Used 3 rd party IP HDMI TX None Many peripheral FPGA ? 8

  9. Fea eature o e of Zynq ynq & V210 S Sys ystem em Accelerated Design Productivity Reduced Time To Market – Fixed processor system with large set of built in peripherals – Standardizing on AMBA-4 AXI enhances portability of IPs – Scalable optimized architecture for IP re-use; AXI interfaces for plug & play IP – Accelerate development with targeted design platforms Increased Time In Market – Software and hardware re-programmability – Field upgradable – Address Processor/ASSPs short shelf life * In the Xilinx doc excerpt 9

  10. Why is Zynq?  Similar CPU  Similar S/W development environment  One chip solution  Long period of EOL How effectively the Zynq system will be able to replace the V210 system? One solution is rapid prototype test. 10

  11. Main concept 1. Find classified AP(ex Samsung V210) products that can be replaced by Zynq. 2. Fix the specification of the PS area is used in common.  Basic development environment (include Linux) can be development without significant change even if the PL is changed  Linux hardware development and porting, a development environment that can save setup time. 3. The PL area is used to change to suit your needs.  Designed to take full advantage of the Xilinx AXI-IP .  In addition to the development of PL added to the area do not need to set up a new linux environment and development  PL area validation verifies fast as bare-metal c code. 11

  12. Main concept 1. Find classified AP(ex Samsung V210) products that can be replaced by Zynq. Embedded System Display Test Equipment Extended peripheral Part Part LCD Equip. Open/Short AFC System Medical Device Display Port Node Inspection Equipment Railway Gateway Patient Monitor (2K, 4K) (FVMI,FIMV Inspection) X-Ray Equipment (Panorama, Ultrasonic) Gateway Device DPS Control Power Control & Trace Multi-Port communication & Wired and Calibration & Measuring Logic Wireless gateway via dedicated protocols AP System Education/IoT Part Education Course FPGA Arduino Training Board 12

  13. Main concept 2. Fix the specification of the PS area is used in common.  Basic development environment (include Linux) can be development without significant change even if the PL is changed  Linux hardware development and porting, a development environment that can save setup time.  Fixed PS area  ARM Cortex-A9 Core  DDR3 1GB x32  SD/MMC  USB 2.0 OTG  1Gbit Ethernet  I2C/UART/SPI/GPIO 13

  14. Main concept 3. The PL area is used to change to suit your needs.  Designed to take full advantage of the Xilinx AXI-IP .  In addition to the development of PL added to the area do not need to set up a new linux environment and development  PL area validation verifies fast as using bare-metal c code. 14

  15. Main concept 3. The PL area is used to change to suit your needs.  Exam 1 : AFC System PL spec  RGB x1 (Used Xilinx Video IP)  UART x8 (Used Xilinx UART IP)  GPIO x8 (Used Xilinx GPIO IP)  PWM x2 (Used Xilinx Timer IP) 15

  16. Main concept 3. The PL area is used to change to suit your needs.  Exam 2 : Display Inspection Equipment PL spec  MCU System (Used Xilinx MicroBlaze IP)  SPI (Used Xilinx QSPI IP)  UART (Used Xilinx UART IP)  RGB x2 (Used Xilinx Video IP)  GPIO x29 (Used Xilinx GPIO IP)  PWM x4 (Used Xilinx Timer IP) 16

  17. Main concept 3. The PL area is used to change to suit your needs.  Exam 3 : Arduino spec  DPRAM for IPC (Used Xilinx IP)  Arduino System (Used FPGArduino platform) * FPGArduino platform website : http://www.nxlab.fer.hr/fpgarduino/  Arduino UNO/MEGA port 17

  18. Implem ement nt the the Des esign : : Exam.1 AF AFC Sys ystem em Zynq PS AXI_UART AXI Interconnect Reset module Video IP AXI_TIMER AXI_GPIO Used Vivado block design tool AXI_EPC 18

  19. Implem ement nt the the Des esign : : Exam.1 AF AFC Sys ystem em Video IP block AXI Interconnect AXI_VTC AXI VMDA Subset Converter AXI_Video Out Used Vivado block design tool 19

  20. Imple lemen ent t t the D Design gn : Exam.2 2 Display AXI Interconnect Zynq PS Video IP Video IP Reset module AXI_TIMER AXI_GPIO AXI_REG Used Vivado block design tool MicroBlaze, UART, SPI 20

Recommend

FPGA What is a FPGA? How FPGAs work How do they work? Manufacturers

FPGA What is a FPGA? How FPGAs work How do they work? Manufacturers

2/21/2012 Content FPGA What is a FPGA? How FPGAs work How do they work? Manufacturers Distributed RAM History FPGA vs ASIC FPGA and Microprocessors Alternatives to FPGAs ETI135, Advanced Digital IC Design

123 views • 10 slides
WWW.FPGA What is an FPGA? Field Programmable Gate Array Introduction to FPGA designs

WWW.FPGA What is an FPGA? Field Programmable Gate Array Introduction to FPGA designs

WWW.FPGA What is an FPGA? Field Programmable Gate Array Introduction to FPGA designs Generic logic cells + Programmable switches Why do we use it? High performance & Flexible Shorter time to market Joachim Rodrigues

308 views • 8 slides
An introduction to FPGA-based acceleration of neural networks Marco Pagani 1 What is an FPGA?

An introduction to FPGA-based acceleration of neural networks Marco Pagani 1 What is an FPGA?

An introduction to FPGA-based acceleration of neural networks Marco Pagani 1 What is an FPGA? Field-programmable gate array (FPGA) are integrated circuits designed to be con fi gured after manufacturing for implementing arbitrary logic

429 views • 15 slides
FPGA language ( HDL ). Overview 3 4 Component-Based Software Design LMES Component-Based

FPGA language ( HDL ). Overview 3 4 Component-Based Software Design LMES Component-Based

11/05/2016 Agenda The topics that will be addressed are: Overview on basic characteristics of the FPGA; Scheduling tasks on Reconfigurable FPGA reconfiguration capabilities; FPGA architectures Timing analysis for reconfigurable

299 views • 10 slides
Tips about an FPGA 02/09/2018 J.C. special topic FPGA ( field-programmable gate array ) FPGA :

Tips about an FPGA 02/09/2018 J.C. special topic FPGA ( field-programmable gate array ) FPGA :

Tips about an FPGA 02/09/2018 J.C. special topic FPGA ( field-programmable gate array ) FPGA : An integrated circuit (IC) designed to be configured by customer or designer after manufacturing -- Developed in ~80s -- Widely used (customer

303 views • 7 slides
GRVI Phalanx Update: A Massively Parallel RISC-V FPGA Accelerator Framework Jan Gray |

GRVI Phalanx Update: A Massively Parallel RISC-V FPGA Accelerator Framework Jan Gray |

GRVI Phalanx Update: A Massively Parallel RISC-V FPGA Accelerator Framework Jan Gray | jan@fpga.org | http://fpga.org CARRV2017: 2017/10/14 FPGA Datacenter Accelerators Are Almost Mainstream Catapult v2. Intel += Altera. OpenPOWER CAPI. AWS

508 views • 28 slides
Support of Cross Calls between Microprocessor and FPGA in CPU-FPGA Coupling Architecture G.

Support of Cross Calls between Microprocessor and FPGA in CPU-FPGA Coupling Architecture G.

Support of Cross Calls between Microprocessor and FPGA in CPU-FPGA Coupling Architecture G. NguyenThiHuong and Seon Wook Kim Microarchitecture and Compiler Laboratory School of Electrical Engineering Korea University Motivation

416 views • 19 slides
FPGA vs GPU Performance Comparison on the Implementation of FIR Filters FPGA. While comparing the

FPGA vs GPU Performance Comparison on the Implementation of FIR Filters FPGA. While comparing the

FPGA vs GPU Performance Comparison on the Implementation of FIR Filters FPGA. While comparing the performance of them, we Abstract choose different models for each platform to get fairer FIR filters find place in digital signal processing

569 views • 7 slides
The Spartan 3e FPGA The Spartan 3e FPGA Whats inside the chip? How does it implement

The Spartan 3e FPGA The Spartan 3e FPGA Whats inside the chip? How does it implement

The Spartan 3e FPGA The Spartan 3e FPGA Whats inside the chip? How does it implement random logic? What other features can you use? What do all these things mean? LUT, Slice, BRAM, DCM, IOB, CLB... Two important documents

278 views • 11 slides
Public FPGA based DM Public FPGA based DMA Atta A Attacking king UlfFrisk Agenda Background

Public FPGA based DM Public FPGA based DMA Atta A Attacking king UlfFrisk Agenda Background

Public FPGA based DM Public FPGA based DMA Atta A Attacking king UlfFrisk Agenda Background and Previous work Transmit and Receive PCIe TLPs DUMP memory FPGA Design Attack vulnerable vanilla Linux system Attack vulnerable UEFI Windows

359 views • 19 slides
Tsunami simulation on FPGA/GPU Tsunami simulation on FPGA/GPU and its analysis based on Statistical

Tsunami simulation on FPGA/GPU Tsunami simulation on FPGA/GPU and its analysis based on Statistical

Tsunami simulation on FPGA/GPU Tsunami simulation on FPGA/GPU and its analysis based on Statistical Model Checking Masahiro Fujita VLSI Design and Education Center (VDEC) University of Tokyo 1 2 Outline What Tsunami simulation means in

1.25k views • 44 slides
Fast FPGA prototyping with Software Development Kit for FPGA (SDK4FPGA) Andrea Suardi

Fast FPGA prototyping with Software Development Kit for FPGA (SDK4FPGA) Andrea Suardi

Fast FPGA prototyping with Software Development Kit for FPGA (SDK4FPGA) Andrea Suardi cas.ee.ic.ac.uk/projects/SDK4FPGA This research has been supported by EPSRC Impact Acceleration grant number EP/K503733/1 Outline What is SDK4FPGA ?

287 views • 18 slides
DMA implementations for FPGA- based data acquisition systems Presenter: Wojciech M. Zabootny

DMA implementations for FPGA- based data acquisition systems Presenter: Wojciech M. Zabootny

DMA implementations for FPGA- based data acquisition systems Presenter: Wojciech M. Zabootny Institute of Electronic Systems Warsaw University of Technology XL-th IEEE-SPIE Joint Symposium Wilga 2017 1/23 FPGA in DAQ FPGA chips are a

656 views • 23 slides
Contents Introduction Pipelined FPGA DNN accelerators Roof-line Model and optimizing

Contents Introduction Pipelined FPGA DNN accelerators Roof-line Model and optimizing

FPGA implementation of Quantized (Deep) Neural Network (QNN) Accelerators Biruk Seyoum Phd Student, Scoula Superiore SantAnna, Pisa Contents Introduction Pipelined FPGA DNN accelerators Roof-line Model and optimizing FPGA DNN

587 views • 23 slides
Processor Architecture Charles Eric LaForest J. Gregory Steffan ECE, University of Toronto FPGA

Processor Architecture Charles Eric LaForest J. Gregory Steffan ECE, University of Toronto FPGA

Octavo: An FPGA-Centric Processor Architecture Charles Eric LaForest J. Gregory Steffan ECE, University of Toronto FPGA 2012, February 24 Easier FPGA Programming We focus on overlay architectures Nios, MicroBlaze, Vector Processors

519 views • 38 slides
FPGA security Nele Mentens nele.mentens@kuleuven.be Design and security of cryptographic

FPGA security Nele Mentens nele.mentens@kuleuven.be Design and security of cryptographic

FPGA security Nele Mentens nele.mentens@kuleuven.be Design and security of cryptographic algorithms and devices for real-world applications June 1-6, 2014, ibenik , Croatia Outline Introduction FPGA vs. ASIC FPGA application

443 views • 17 slides
RTLinux in an FPGA Alejandro Lucero alucero@os3sl.com www.os3sl.com RTLinux in a FPGA 1.

RTLinux in an FPGA Alejandro Lucero alucero@os3sl.com www.os3sl.com RTLinux in a FPGA 1.

RTLinux in an FPGA Alejandro Lucero alucero@os3sl.com www.os3sl.com RTLinux in a FPGA 1. OpenRTU Project 2. FPGAs and soft processors 3. uClinux 4. RTLinux in Microblaze www.os3sl.com RTLinux in a FPGA 1. OpenRTU Project Spanish

378 views • 33 slides
Memories Introduction Why do we need memory in an FPGA Device? Topics Types of FPGA

Memories Introduction Why do we need memory in an FPGA Device? Topics Types of FPGA

Memories Introduction Why do we need memory in an FPGA Device? Topics Types of FPGA Memories Available Resources Realizing memories in an HDL design Applications Examples Extra: Memory Controller Block Memories

692 views • 10 slides
Experience with FPGA HDK AMI and F1: (all statements are subject to large systematic

Experience with FPGA HDK AMI and F1: (all statements are subject to large systematic

Experience with FPGA HDK AMI and F1: (all statements are subject to large systematic uncertainties) Nhan SDA CCEL 2 PC Write host code Memory runs on CPU CPU PCI communicates through PCIe, Express must be streaming (AXI) FPGA

354 views • 13 slides
FPGA%Timing%Models Many%FPGA%and%CPLD%vendors%provide%a% timing model

FPGA%Timing%Models Many%FPGA%and%CPLD%vendors%provide%a% timing model

FPGA%Timing%Models Many%FPGA%and%CPLD%vendors%provide%a% timing model in%their%data%sheets%that%allow% estimation%of%path%delays. Some%example%path%delays%that%are%of%interest: Minimum%Pin%to%Pin%(combinational)%delay%

361 views • 23 slides
Current Trends in Hybrid FPGA/CPU Devices Hybrid FPGA/CPU Devices Xilinx Zynq Series Real

Current Trends in Hybrid FPGA/CPU Devices Hybrid FPGA/CPU Devices Xilinx Zynq Series Real

Current Trends in Current Trends in Hybrid FPGA/CPU Devices Hybrid FPGA/CPU Devices Xilinx Zynq Series Real Innovation or Temporary Hype? Stephanie Rupprich Introduction Stephanie Rupprich FPGA Embedded Processors Heidelberg

611 views • 43 slides
On the Sensitivity of FPGA Architectural Conclusions to Experimental Assumptions, Tools, and

On the Sensitivity of FPGA Architectural Conclusions to Experimental Assumptions, Tools, and

On the Sensitivity of FPGA Architectural Conclusions to Experimental Assumptions, Tools, and Techniques Andy Yan, Rebecca Cheng, Steve Wilton University of British Columbia Vancouver, B.C. stevew@ece.ubc.ca FPGA Experiments: Impressive

654 views • 49 slides
FPGA-CAPELLA: A REAL TIME AUDIO FX UNIT COSMA KUFA AND JUSTIN XIAO WHAT IS FPGA-CAPELLA?

FPGA-CAPELLA: A REAL TIME AUDIO FX UNIT COSMA KUFA AND JUSTIN XIAO WHAT IS FPGA-CAPELLA?

FPGA-CAPELLA: A REAL TIME AUDIO FX UNIT COSMA KUFA AND JUSTIN XIAO WHAT IS FPGA-CAPELLA? FPGA-capella is an audio FX unit Allows users to apply interesting audio FX to their sound Offers flexibility Gives musicians an interesting

379 views • 11 slides
Andrew Clinton, Matt Liberty, Ian Kuon FPGA Routing (Interconnect) FPGA routing consists of a

Andrew Clinton, Matt Liberty, Ian Kuon FPGA Routing (Interconnect) FPGA routing consists of a

Andrew Clinton, Matt Liberty, Ian Kuon FPGA Routing (Interconnect) FPGA routing consists of a network of wires and programmable switches Wire is modeled with a reduced RC network Drivers are modeled as a SPICE netlist 2-Level pass

673 views • 20 slides

More recommend