Fabrication of ATLAS pixel detector prototypes at IRST M. Boscardin, G.-F. Dalla Betta, P. Gregori, M. Zen, N. Zorzi Centro per la Ricerca Scientifica e Tecnologica (ITC-irst), Località Pantè di Povo, 38050 Trento, Italy M. Boscardin June 5 - 8, 2000 Pixel 2000, Genova
Outline • Introduction • Description of the fabrication technology • Fabrication of 1 st and 2 nd prototypes: experimental results and problems • Conclusions M. Boscardin June 5 - 8, 2000 Pixel 2000, Genova
Introduction • In the last few years, IRST has been involved in the development of silicon microstrip detector technologies within an R&D project supported by INFN. • Starting from fall 1998, we have fabricated silicon pixel detectors oriented to the ATLAS experiment (prototypes 1 and 2). • We present the main processing issues and report some selected results from the electrical characterization of detectors and test structures carried out before detector delivery. M. Boscardin June 5 - 8, 2000 Pixel 2000, Genova
Process/Layout Constraints PROCESS IRST microstrip n-on-n pixel detector develop technology isolation with p-spray a new process p-stop (or moderated p-spray) LAYOUT RULES BIAS dot IRST microstrip tech. overlap n + -region and p + -region no overlap between overlap contact hole and n + - region n&p regions M. Boscardin June 5 - 8, 2000 Pixel 2000, Genova
Process Flow (1/3) initial oxide growth (200nm) p-spray implantation B 4.5E12 70KeV resist define moderated p-spray moderated p-spray implantation B 4.5E12 70KeV TEOS TEOS deposition (800nm) termal oxide M. Boscardin June 5 - 8, 2000 Pixel 2000, Genova
Process Flow (2/3) define p + region implant oxide growth (40nm) p + implant (B 5E14 70KeV) define n + region p + drive-in (900°C in dryO 2 ) n + implant (P 5E15 120KeV) n + drive-in (975°C in dryO 2 ) TEOS deposition (300nm) low temperature annealing M. Boscardin June 5 - 8, 2000 Pixel 2000, Genova
Process Flow (3/3) define and open contact holes (n&p side) metal deposition (1 µ m Al 1%Si) 1 st LTO deposition (500nm) define metal (n-side) etch LTO and metal 1 st LTO 2 nd LTO deposition (500nm) 2 nd LTO define metal (p-side) etch LTO and metal 3 rd LTO deposition (500nm) 3 rd LTO define and open passivation (n&p side) sintering M. Boscardin June 5 - 8, 2000 Pixel 2000, Genova
Detector Fabrication: critical steps moderated p-spray two separate implantations p-spray = blank + moderated p-spray = p-stop like p + and n + region implantation through a screen oxide using a thick oxide layer as implant mask low temperature annealing increase gettering efficiency metal and passivation LTO oxide to protect metal layer M. Boscardin June 5 - 8, 2000 Pixel 2000, Genova
= = Prototype 1: Experimental results Test Structures diode 4mm 2 I leak ≅ ≅ 300pA @ full depletion ≅ ≅ gated diode s 0 ≅ ≅ = ≅ ≅ = 30 cm/sec 1.0E-07 diode Leakage Current [A] guard-ring 1.0E-08 1.0E-09 1.0E-10 1.0E-11 0 200 400 600 800 Bias Voltage [V] IV curves of multiguard diode (area 2.2mm 2 ) M. Boscardin June 5 - 8, 2000 Pixel 2000, Genova
Prototype 1: Experimental results 1.0E-04 V bk at low voltage (about 20V) Single Chip Current [A] probably due to a misalignement 1.0E-05 between contact and n-diff region 1.0E-06 I back I p-spray 1.0E-07 Number of Single Chip [%] 35 30 1.0E-08 25 I back 20 1.0E-09 15 0 20 40 60 80 10 Bias Voltage [V] 5 I back , I p-spray with p-spray @ V=0 0 0 20 40 60 80 100 120 140 160 180 200 I back with p-spray floating Breakdown Voltage [V] M. Boscardin June 5 - 8, 2000 Pixel 2000, Genova
Prototype 2: Experimental results layout NOD LAD overlap between contact and n + region = 2,5 µ m leakage current on single chip (ST SMD) I leak ≅ ≅ 7.5nA @ 50V ≅ ≅ SMD To increase the radiation hardeness of detectors, wafers have been oxygen enriched via a dedicated process step (24h oxidation process at 1150°C). M. Boscardin June 5 - 8, 2000 Pixel 2000, Genova
Single Chip: IV curves 1.E-05 1.E-05 ST LAD ST SMD 1.E-06 1.E-06 Leakage Current [A] Leakage Current [A] 1.E-07 1.E-07 1.E-08 1.E-08 1.E-09 1.E-09 0 50 100 150 200 0 50 100 150 200 Bias Voltage [V] Bias Voltage [V] M. Boscardin June 5 - 8, 2000 Pixel 2000, Genova
Single Chip: V BK & I leak distributions Number of Single Chips [%] 70 Number of Single Chips [%] 25 ST LAD 60 ST NOD 20 ST LAD 50 ST SMD ST SMD 15 40 30 10 20 5 10 0 0 0 30 60 90 120 150 180 210 240 270 1000 0 20 40 60 80 100 120 140 160 180 200 Leakage Current @ 100V [nA] Breakdown Voltage [V] Average Leakage Current @ 100V of ST SMD & LAD Breakdown of ST NOD < 140V about 30 nA M. Boscardin June 5 - 8, 2000 Pixel 2000, Genova
Tiles: IV curves 1.E-04 1.E-04 SMD LAD 1.E-05 Leakage Current [A] Leakage Current [A] 1.E-05 1.E-06 1.E-06 1.E-07 1.E-07 1.E-08 1.E-08 0 25 50 75 100 125 150 175 200 0 25 50 75 100 125 150 175 200 Bias Voltage [V] Bias Voltage [V] M. Boscardin June 5 - 8, 2000 Pixel 2000, Genova
Tiles: Breakdown Voltage Distributions 60 Tiles with a V BK >150V NOD 50 Number of detectors [%] NOD 0 SMD LAD SMD 8 40 LAD 4 30 Tiles with a V BK = 20V 20 NOD 10 SMD 7 10 LAD 15 0 0 20 40 60 80 100 120 140 160 180 200 Breakdown Voltage [V] M. Boscardin June 5 - 8, 2000 Pixel 2000, Genova
Conclusions • We have processed some prototype batches of silicon pixel detector oriented to the ATLAS experiment. • To this purpose, a dedicated technology has been developed. • The electrical characterization of single chips and related test structures have evidenced that IRST technology is potentially adequate for the fabrication of these detectors. • However, results from tiles measurements have shown that the number of process-related defects should be decreased in order to fulfill the detector specifications (in particular in terms of breakdown voltage) with a satisfactory fabrication yield. M. Boscardin June 5 - 8, 2000 Pixel 2000, Genova
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