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Apr 16, 2023 •773 likes •1.18k views

Vladimir S. Podosinov ece BRADLEY DEPARTMENT of ELECTRICAL & COMPUTER ENGINEERING Motivation for the project Other devices on the market Transceiver structure and design Testing Results Conclusions and Future Work

  1. Vladimir S. Podosinov ece BRADLEY DEPARTMENT of ELECTRICAL & COMPUTER ENGINEERING

  2.  Motivation for the project  Other devices on the market  Transceiver structure and design  Testing Results  Conclusions and Future Work  Questions ece BRADLEY DEPARTMENT of ELECTRICAL & COMPUTER ENGINEERING

  3. Suppose there are 3 different information channels that need to be received at the same time - Different bandwidths - Different modulations 0 -5 -10 -15 Power (dB) -20 -25 -30 ece -35 -40 0 5 10 15 20 25 30 35 40 45 50 Frequency (Hz) Fs = 100 BRADLEY DEPARTMENT of ELECTRICAL & COMPUTER ENGINEERING

  4. f 1 f 1 f 2 f 2 Transmitter Receiver f 3 f 3  Instead of wideband antenna, a narrowband antenna with tunable frequency can be used, and hop between frequencies quickly  Need to see if performance drops due to frequency hopping. Need bit error rate (BER) testing platform ece BRADLEY DEPARTMENT of ELECTRICAL & COMPUTER ENGINEERING

  5.  A good way to test system is to use software defined radio (SDR) o Can implement any modulation o Can modify platform at any time ece BRADLEY DEPARTMENT of ELECTRICAL & COMPUTER ENGINEERING

  6.  Software defined radio is independent of the components, adding a new capability, becomes writing a new firmware, not building a new device. ece Software Defined Radio in the Ideal Case BRADLEY DEPARTMENT of ELECTRICAL & COMPUTER ENGINEERING

  7. Current SDRs on the Market ece BRADLEY DEPARTMENT of ELECTRICAL & COMPUTER ENGINEERING

  8.  There are multiple devices that can be used for Software defined radio on the market  Ettus Research has 2 platforms, and recently introduced a new one USRP USRP2 ece BRADLEY DEPARTMENT of ELECTRICAL & COMPUTER ENGINEERING

  9.  There is also a Rice University WARP (Wireless Open-Access Research Platform)  And there is a commercial product from Lyrtech  ComBlock also has some modules that implement a modem and are developing SDR platform ece BRADLEY DEPARTMENT of ELECTRICAL & COMPUTER ENGINEERING

  10.  Rice University WARP platform is pretty expensive, and so are products from Lyrtech  Ettus Research is a bargain, and there is a large community supporting it with GnuRadio  ComBlock modules are pre-programmed. Each new feature will require a different block. Or IP (intellectual property) needs to be purchased ece BRADLEY DEPARTMENT of ELECTRICAL & COMPUTER ENGINEERING

  11. Transceiver Structure ece BRADLEY DEPARTMENT of ELECTRICAL & COMPUTER ENGINEERING

  12. ece BRADLEY DEPARTMENT of ELECTRICAL & COMPUTER ENGINEERING

  13. ece BRADLEY DEPARTMENT of ELECTRICAL & COMPUTER ENGINEERING

  14.  Transmitter consist of DSP board, a DAC board, and an up-converter modulator  Modulator range: 950-1450 MHz  DAC: Max sampling rate 125 MSPS; maximum output bandwidth 13 MHz  DSP and DAC are connected together using IDE cable through an external memory interface  External interface memory clock is used for the DAC transfers  At the moment clock rate is 12 MHz ece BRADLEY DEPARTMENT of ELECTRICAL & COMPUTER ENGINEERING

  15.  Receiver consists of down- converter demodulator with the ADCs  FPGA for preprocessing and communication control with the DSP  Down-converter range: 900-1575 MHz  ADC sample rate: 40 MSPS ece BRADLEY DEPARTMENT of ELECTRICAL & COMPUTER ENGINEERING

  16. CLOCK 1 MHz clock ERROR MAX GENERATOR 10 MHz clock RESET ADC CLK AGC DAC CLK AGC DAC 10 ERROR 10 10 10 10 AGC CIC DELAY ADJUST Matched Filter TED 10 I DELAY 10 10 10 Q 10 10 10 10 10 10 MOD TYPE IF FREQUENCY DATA SOURCE FPGA TO DSP 20 TRANSFER HINT MODULE HRDY STROBE SYSTEM CLK FPGA: Xilinx Spartan-3 400 ece BRADLEY DEPARTMENT of ELECTRICAL & COMPUTER ENGINEERING

  17.  DSP Code o Network Communication o Baseband Signal Generation o Signal reception and correction o Error Calculation ece BRADLEY DEPARTMENT of ELECTRICAL & COMPUTER ENGINEERING

  18.  FPGA Code o DC Offset Correction o Automatic Gain Control (AGC) o IF Down conversion and Decimation o Matched Filtering o Timing Correction o DSP Communication ece BRADLEY DEPARTMENT of ELECTRICAL & COMPUTER ENGINEERING

  19. HINT = 1 / HRW = 1 CTRL = 11 HINT = 1 / START HRW = 1 Data <= 2 CTRL = 11 HINT = 0 / HRW = 0 CTRL = 00 HINT = 0 / HINT = 0 / HRW = 0 HRW = 0 EXIT CTRL = 00 INTACK CTRL = 10 Data => 4 Data => 4 HINT = 0 / HINT = 1 / HINT = 1, HRW = 1, HRW = 0 HRW = 0 DATA[1] = 1 / CTRL = 00 CTRL = 10 HRW = 1 CTRL = 00 WADDR HRDY = 1 / HINT = 1, HRW = 1, CPUWAIT Data => HRW = 1 HINT = 1, HRW =0 / DATA[1] = 0 / Data => 2 Addr1/Addr2 CTRL = 10 HRW = 1 HRW = 0 Data <= DSP_IN CTRL = 00 CTRL = 10 HRDY = 0 / DATA_CNT = 255 / WDATA HRW = 0 HRW = 0 Data => CTRL = 01 ece CTRL = 01 Samples DATA_CNT < 255 / HRW = 0 BRADLEY DEPARTMENT of ELECTRICAL & COMPUTER ENGINEERING CTRL = 01

  20.  Linear Feedback Shift Register (LFSR)  LFSRs are used to generate maximal length sequences (m-sequence) ece BRADLEY DEPARTMENT of ELECTRICAL & COMPUTER ENGINEERING

  21.  BIOS is the real-time operating system (RTOS) used in some of the TI’s DSPs  Advantages of the BIOS over traditional coding is the use of scheduler ece BRADLEY DEPARTMENT of ELECTRICAL & COMPUTER ENGINEERING

  22. ece BRADLEY DEPARTMENT of ELECTRICAL & COMPUTER ENGINEERING

  23. Code without BIOS Code with BIOS ISR() { ISR() { Call SWI(); Interrupt triggered code } } main() { Call setup functions; main() { return; while(1) { } Functions(); SWI() { Other code; Process interrupt here; } } } OtherThread() { Perform other code; ece } BRADLEY DEPARTMENT of ELECTRICAL & COMPUTER ENGINEERING

  24. Test Results ece BRADLEY DEPARTMENT of ELECTRICAL & COMPUTER ENGINEERING

  25. RBW 100 kHz Delta 2 [T1 ] VBW 300 kHz -26.45 dB Ref 5 dBm * Att 0 dB SWT 2.5 ms -1.008012821 MHz Marker 1 [T1 ] 0 -24.95 dBm 1.449959936 GHz A Delta 3 [T1 ] -10 1 SA -26.00 dB AVG 1.009615385 MHz -20 1 -30 -40 2 3 SWP 64 of 64 -50 3DB -60 -70 -80 -90 Center 1.45 GHz 500 kHz/ Span 5 MHz RBW 100 kHz Marker 4 [T1 ] VBW 300 kHz -55.95 dBm Ref 5 dBm * Att 0 dB SWT 2.5 ms 1.448493590 GHz Marker 1 [T1 ] 0 -16.21 dBm 1.450456731 GHz A Marker 2 [T1 ] 1 SA -10 -16.90 dBm 1 AVG 2 1.449447115 GHz Marker 3 [T1 ] -20 -55.33 dBm 1.451418269 GHz -30 -40 SWP 64 of 64 -50 3DB 3 4 -60 -70 ece -80 -90 Center 1.45 GHz 500 kHz/ Span 5 MHz BRADLEY DEPARTMENT of ELECTRICAL & COMPUTER ENGINEERING

  26. RBW 100 kHz Delta 2 [T1 ] VBW 300 kHz -42.36 dB Ref 5 dBm Att 0 dB SWT 2.5 ms -1.008012821 MHz * Marker 1 [T1 ] 0 -13.32 dBm 1.449959936 GHz A Delta 3 [T1 ] -10 1 1 SA -40.00 dB AVG 1.009615385 MHz -20 -30 -40 SWP 64 of 64 3 -50 3DB 2 -60 -70 -80 -90 Center 1.45 GHz 500 kHz/ Span 5 MHz RBW 100 kHz Delta 4 [T1 ] VBW 300 kHz -3.45 dB Ref 5 dBm * Att 0 dB SWT 2.5 ms -3.012820513 MHz Marker 1 [T1 ] 0 -22.77 dBm 1.451458333 GHz A Delta 2 [T1 ] 1 SA -10 -0.15 dB AVG -1.995192308 MHz Delta 3 [T1 ] 2 1 -20 -2.82 dB 3 4 -969.551282051 kHz -30 -40 SWP 64 of 64 -50 3DB -60 -70 ece -80 -90 Center 1.45 GHz 500 kHz/ Span 5 MHz BRADLEY DEPARTMENT of ELECTRICAL & COMPUTER ENGINEERING

  27. QPSK 16-QAM ece BRADLEY DEPARTMENT of ELECTRICAL & COMPUTER ENGINEERING

  28. 8-PAM 16-APSK ece BRADLEY DEPARTMENT of ELECTRICAL & COMPUTER ENGINEERING

  29. -1 10 BPSK/QPSK Theory BPSK Measured QPSK Measured BASK Theory BASK Measured -2 10 -3 10 Bit Error Rate -4 10 -5 10 ece -6 10 3 4 5 6 7 8 9 10 E b /N 0 (dB) BRADLEY DEPARTMENT of ELECTRICAL & COMPUTER ENGINEERING

  30. -1 10 8-PSK Theory 8-PSK Measured 16-QAM Theory 16-QAM Measured 16-APSK Theory 16-APSK Measured -2 10 Bit Error Rate -3 10 -4 10 ece -5 10 5 6 7 8 9 10 11 12 E b /N 0 (dB) BRADLEY DEPARTMENT of ELECTRICAL & COMPUTER ENGINEERING

  31. 4-ASK Theory 4-ASK Measured 8-PAM Theory 8-PAM Measured -1 10 Bit Error Rate ece -2 10 3 4 5 6 7 8 9 10 E b /N 0 (dB) BRADLEY DEPARTMENT of ELECTRICAL & COMPUTER ENGINEERING

  32. ece BRADLEY DEPARTMENT of ELECTRICAL & COMPUTER ENGINEERING

  33. ece BRADLEY DEPARTMENT of ELECTRICAL & COMPUTER ENGINEERING

  34. Modulation Error Test 1 Error Test 2 BASK 0.01643164 0.0122165 BPSK 0.0152784 0.01331759 QPSK 0.0072194 0.0188586 4-ASK 0.014609 0.014479 8-PAM 0.032588 0.032715 8-PSK 0.047863 0.0271668 16-QAM 0.0323732 0.024467 ece 16-APSK 0.0248244 0.025308 BRADLEY DEPARTMENT of ELECTRICAL & COMPUTER ENGINEERING

  35. Modulation Error Test 1 Error Test 2 BASK 0.0165107 0.0164654 BPSK 0.0138805 0.0130997 QPSK 0.021261 0.0235587 4-ASK 0.023284 0.020410 8-PAM 0.0367070 0.03299138 8-PSK 0.030490 0.0347004 16-QAM 0.0252258 0.02521068 ece 16-APSK 0.027396438 0.02745781 BRADLEY DEPARTMENT of ELECTRICAL & COMPUTER ENGINEERING

  36. Conclusions and Future Work ece BRADLEY DEPARTMENT of ELECTRICAL & COMPUTER ENGINEERING

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