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Physical Design Issues in Biofluidic Microchips Tamal Mukherjee - PowerPoint PPT Presentation

Physical Design Issues in Biofluidic Microchips Tamal Mukherjee MEMS Laboratory ECE Department ECE Department Carnegie Mellon University Pittsburgh, PA, USA tamal@ece.cmu.edu http://www ece cmu edu/~mems http://www.ece.cmu.edu/ mems


  1. Physical Design Issues in Biofluidic Microchips Tamal Mukherjee MEMS Laboratory ECE Department ECE Department Carnegie Mellon University Pittsburgh, PA, USA tamal@ece.cmu.edu http://www ece cmu edu/~mems http://www.ece.cmu.edu/ mems Carnegie Mellon g ISPD, April 16, 2008 ISPD, April 16, 2008

  2. Tubes to Chips: ICs � Driven by Information Processing needs IBM 701 calculator Intel 4004 Calculator IC 2 (1952) (1971)

  3. Tubes to Chips: BioChips � Driven by Biomolecular Analysis needs Image from Barnard College Archives Agilent DNA analysis Test tubes & Beakers (1950) (1950) Lab on a Chip (1997) Lab on a Chip (1997) 3

  4. Portable Analysis y � New knowledge of molecular basis of biology � e.g. Human Genome Project � Massively parallel analysis infrastructure � Integration and miniaturization will drive biomolecular analysis instrumentation Biomolecular Biomolecular S Spock with Tricorder k ith T i d Burns 4 “mainframes” Sensor + computer Science 2002

  5. Typical Biological Lab Functions y g � Synthesis � Analysis A A A + B A + B C C B B A + B A + B Mixing Mixing Reaction Reaction Separation Separation 5

  6. Microdevice Technology Summary gy y BioMEMS Bi Chi BioChips Droplet Droplet Lab-on-a Chip Ch Channel l P Pressure Electrokinetics Electrokinetics 6

  7. Channel-based LoC: EK drive Flow direction � What is Electrokinetics ? � Voltage driven flow V lt d i fl � Why Electrokinetic flow? Wh Electrokinetic flo ? Pressure flow EK flow � Plug velocity profile � Portable kV sources � Portable kV sources � EK flow can be used for electrophoresis p � EK flow already used in complex Serial designs designs Mixer Mixer ORNL 7

  8. Microdevice Technologies: LoC g � Miniaturized Bio-chemical Lab-on-a-Chip � Individual functional units demonstrated � Analyzer, Reactor, … � Research driven by integration � Design aids needed to handle complexity! Design aids needed to handle complexity! Immunoassay Amino-Acid Chemical DNA Analysis Analysis y Synthesis y ORNL U. Hull U. C. Berkeley U. Alberta 8

  9. Outline � Introduction � Motivation for Design Automation � Design Hierarchy g y � Multi-function System Simulation � Multi plex Physical Synthesis � Multi-plex Physical Synthesis � Summary 9

  10. Multiplex Lab-on-a-Chip � Same subsystem, integrated for redundancy, combinatorial experiments bi t i l i t integration 10 year

  11. Multifunction LoCs Example: Immunoassay loading reagent 1 Load sample {Ag* Ag} 1. Load sample {Ag*, Ag} 2. Mix with reagents {Ab} mixing mixing 3. Rxn: Ag* + Ab � Ag*-Ab A * + Ab � A * Ab 3 R 4. Inject sample plug reaction 5. Separate analytes S t l t buffer 6. Detection injection { [Ag* Ag] Ab Ag*-Ab} { [Ag ,Ag], Ab, Ag -Ab} sample separation p waste waste detection buffer waste 11

  12. Complexity Hierarchy y y Element Element Functional Functional Subsystem Subsystem System System Component Increasing Integration 12

  13. Outline � Introduction � Motivation for Design Automation � Design Hierarchy g y � Multi-function System Simulation � Multi plex Physical Synthesis � Multi-plex Physical Synthesis � Summary 13

  14. Simulation Techniques � Computational fluid dynamics buffer buffer B B B B uf f er uf f er uf f er uf f er Complimentary turns One single turn S S am am pl e pl e sample Flow direction Flow direction ~ 10 Hours 2~3 days ~ 10 hours � Reduced order models educed o de ode s Serial � Hierarchical decomposition Mixer and parameterization p (ORNL) (ORNL) � Capture geometric effects � Amenable for use in design 14

  15. Hierarchy Example: Immunoassay y y Sample Buffer V+ Ag* Ag Ag , Ag V+ V+ V+ V+ Flow Direction V- Mixing and Reaction g Sample Waste Ag* + Ab � Ag*-Ab Pinching Ab Ag*, Ag, Ab, V+ V+ Ag*-Ab Ag Ab Buffer Buffer V+ Waste 15

  16. Synthesis Phase: Steady State y y Buffer V+ V+ V+ Flow Direction V- Mixing and Reaction g Sample Waste Ag* + Ab � Ag*-Ab Pinching Ag*, Ag, Ab, V+ Ag*-Ab Ag Ab Buffer Buffer V+ Waste 16

  17. Analysis Phase: Transient y Buffer V+ V- V- Flow Direction V- Sample Plug Sample Plug Sample Waste Mixture of Ag*, Ag, Ab, Ag*-Ab V- on Separatio l Channe S Buffer Buffer V- Waste 17

  18. Analysis Phase: Transient y Buffer V+ V- V- Flow Direction V- Sample Waste V- on Separatio l Channe Ag*-Ab Ab S Ag*,Ag distance apart p Buffer Buffer Resolution = R l ti V- band broadness Waste 18

  19. Component Library Library of LoC Unit Compose Topology Compose Topology Operations Function Function Type Type well mixer mixer reactor injector separator splitter 19

  20. Composition Examples Buffer A B Sample Sample waste Serpentine separation chip (ORNL) hi (ORNL) Multi-stream mixer (M. Koch, et al.) M lti t i (M K h t l ) System waste aste ste-1 Buffer System waste Sample wa Was Buffer B S e Sample A 1 A 2 A 3 A 4 A 5 Sample Waste 2 Waste-2 Spiral chip Serial Mixing network (S.C. Jacobson, et al.) 20 (ORNL)

  21. Outline � Introduction � Motivation for Design Automation � Design Hierarchy g y � Component Models � Multi function System Simulation � Multi-function System Simulation � Multi-plex Physical Synthesis � Summary 21

  22. Simulating a Multifunction Design g g (Cheim, Clin. Chem., 44:3 , 591-598, 1998) � Real Immunoassay Chip from U. Alb Alberta t � Operation � Mixing/Dilution g � Reaction � Injection j � Separation � Detection 22 Wang et. al. Transducers ‘05

  23. Simulation Results Calibration curve 10 mm after injection 10 mm after injection 10 mm after injection Schematic Schematic 1.0 1.0 Ag Ag* Th * Th * Th Th Experimental Experimental E E i i l l 0.8 0.8 ntration c ntration c ntration c ntration c a ratio a ratio 0.6 0.6 Before turn Before turn Before turn Ag* Ag Area Area elative concen elative concen elative concen elative concen Th * Th * Th * Th * 0.4 0.4 Ab-Ag* Ab-Ag* Ab-Th * Ab-Th * Th * -Ab complex Th * -Ab complex 0.2 0.2 Re Re Re Re After turn After turn After turn 0.0 0.0 0 0 10 10 20 20 30 30 40 40 Antigen (Ag) (mg/L) Antigen (Ag) (mg/L) Theophylline Th (mg/L) Theophylline Th (mg/L) Theophylline Th (mg/L) Theophylline Th (mg/L) 0 0 0 0 5 5 5 5 10 10 10 10 15 15 15 15 20 20 20 20 25 25 25 25 30 30 30 30 35 35 35 35 Time (s) Time (s) Time (s) Time (s) Electropherogram � Ag ↑ ⇒ unreacted Ag* ↑ ⇒ Ab-Ag* ↓ � Simulation matches experiment � Simulation matches experiment � Simulation time is a few CPU seconds 23 Wang et. al. Transducers ‘05

  24. Optimizing the design: NLP g g x 0 x x obj bj : : min i f f ( ( y ) ) i i i = y SIM ( x , PARAMS ) < s . t . g ( y ) 0 i i y = = i h h ( ( y y ) ) 0 0 i x 7.6 cm * 10x less space 0.75 cm mixer S Same perf f 2 cm 1.22 cm detector separation reactor injector channel 1.73 cm 1.14 cm 7.6 cm 2.23 cm 7 2.33 cm 24 2.5 cm Wang et. al. Transducers ‘05

  25. Outline � Introduction � Motivation for Design Automation � Design Hierarchy g y � Multi-function System Simulation � Multi plex Physical Synthesis � Multi-plex Physical Synthesis � Summary 25

  26. Multiplex Physical Synthesis y y Family of subsystems Simultaneously determine: � placement � dimensions � # of sections Input: Design Specs � voltage voltage � Overall Chip Dimensions � Species/Buffer properties Intermediate Placement � Operational constraints � Operational constraints � Chip fabrication � Subsystem performance Final Routed Layout Route subsystems to wells: � single layer, planar 26 � min. length, bends Pfeiffer et. al., TCAD ‘06

  27. Placement Features � Subsystem optimization: NLP � � “System-on-Chip” extensions * : e e a d a d c t s s c c b * Murata, H. et al., IEEE Trans. on CAD. 1996 b f f � Orientation: � Orientation: and E T � Well placement: e e a e d a d a d c E L E R c c f b b b b b f f f f � Overlap constraints: E B e Penalty � Penalty � Never � Never � a a a a d d c b 27 b f Pfeiffer et. al., TCAD ‘06

  28. Routing Features g � Routing grid graph * : e e e a a d d Expand Expand a a d d c c * Lengauer, T., Combinatorial Algs. for IC Layout, 1990 b b f f f f 7 8 9 flows in = flows out fl i fl t � Node constraints: 4 5 6 1 flow in/out of node (single layer, planar) (single layer, planar) 1 2 3 +1 7 8 9 +1 +1 penalize bends � Bend reduction: 4 5 6 favor straight paths favor straight paths +0 +0 1 2 3 28 Pfeiffer et. al., TCAD ‘06

  29. Multiplex Synthesis Example y Placed and Routed Design P&R By Hand Automated Improvement Place: Place: 20 min 20 min Route: 3 min 5+ hrs. > 10X faster Time Total: 23 min Dimensions Di i 1 67 1.67cm x 8.8cm 8 8 1 61 1.61cm x 3.79cm 3 79 ~ 2.5X smaller 2 5X ll 29 Pfeiffer et. al., TCAD ‘06

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