Fei Li and Lei He Li and Lei He Fei ECE Dept. ECE Dept. - PowerPoint PPT Presentation

Fei Li and Lei He Li and Lei He Fei ECE Dept. ECE Dept. University of Wisconsin – – Madison Madison University of Wisconsin http://eda.ece.wisc.edu http://eda.ece.wisc.edu

� Maximum Current Affects Power/Ground wires Maximum Current Affects Power/Ground wires � – Electromigration Electromigration – – IR voltage drop IR voltage drop – – Ground bounce Ground bounce – – Ldi Ldi/ /dt dt inductive noise inductive noise – � Excessive Maximum Current may cause Excessive Maximum Current may cause � – Permanent circuit failure Permanent circuit failure – – Logic malfunction Logic malfunction – – Timing error Timing error –

� Previous Work Previous Work � – Find two input vectors that cause maximum switching current Find two input vectors that cause maximum switching current – � Various Approaches Proposed Various Approaches Proposed � – Simulation Simulation- -based based – – ATPG ATPG- -based based –

� The Scaling Trend in Semiconductor Industry The Scaling Trend in Semiconductor Industry � – Scaling down of supply voltage ( Scaling down of supply voltage (Vdd Vdd) ) – – Reduction of transistor threshold voltage to compensate for Reduction of transistor threshold voltage to compensate for – performance loss performance loss � Dynamic Power Dynamic Power � – Offset by the scaling down of Offset by the scaling down of Vdd Vdd – � Leakage Power Leakage Power � – Increases exponentially when threshold voltage scales down Increases exponentially when threshold voltage scales down – – Anticipated to be comparable to dynamic power in a few Anticipated to be comparable to dynamic power in a few – generation generation

� Intel’s microprocessor in the past few technology Intel’s microprocessor in the past few technology � generations generations � Leakage power soon becomes comparable to dynamic Leakage power soon becomes comparable to dynamic � power power

� Sleep transistor to power on or power off the circuit Sleep transistor to power on or power off the circuit � � Power gating reduces leakage power as well as dynamic Power gating reduces leakage power as well as dynamic � power power

� Phenomena: Phenomena: � – All the gate output nodes in the functional unit will All the gate output nodes in the functional unit will – be discharged quickly during sleep mode be discharged quickly during sleep mode – Significant current spike is observed when the Significant current spike is observed when the – functional unit is powered on again functional unit is powered on again � Power Power- -on current is different from normal switching on current is different from normal switching � current current – Dependent on one vector as the initial state is always “0” Dependent on one vector as the initial state is always “0” – – Related to size of sleep transistor and P/G noise Related to size of sleep transistor and P/G noise –

� Assumption Assumption � – The power The power- -on charging current is proportional to on charging current is proportional to – the total charge to be restored after wake- -up up the total charge to be restored after wake � Objective Objective � – Maximize the total stored charge after the Maximize the total stored charge after the – functional unit is powered on functional unit is powered on � Two Algorithms proposed by using ATPG technique Two Algorithms proposed by using ATPG technique � – Fanout Fanout- -based Algorithm based Algorithm Imax/ Imax/Fanout Fanout – – Gain Gain- -based Algorithm based Algorithm Imax/Gain Imax/Gain – – Both are heuristic algorithms Both are heuristic algorithms –

Imax/Fanout � Figure of merit for the maximum current Figure of merit for the maximum current � P VAL ( g ) F ( g ) V = ⋅ ⋅ � i out dd for all the gates is the logic value of gate g g , is the load , is the load is the logic value of gate F out ( g ) VAL ( g ) – – capacitance of gate g g . . capacitance of gate � It is a greedy algorithm It is a greedy algorithm � – Assign logic value 1 to gates in a greedy fashion Assign logic value 1 to gates in a greedy fashion – – Fanout Fanout determines the order of gates to be assigned determines the order of gates to be assigned –

Imax/Fanout (cont) � Test generation technique is used to resolve the Test generation technique is used to resolve the � conflicts and get the input vector conflicts and get the input vector – Backtracing Backtracing to choose the path that may maximize the to choose the path that may maximize the – assignment of value 1 assignment of value 1 – Backtracking to resolve the conflicts Backtracking to resolve the conflicts –

Imax/Gain � The The fanout fanout- -based metric is somewhat local based metric is somewhat local � � Gain Gain defined as the new metric for each gate output to defined as the new metric for each gate output to � observe more globally observe more globally � Gain is computed by Gain is computed by implication implication of the assignment of the assignment � ( v 1 ) V ( h ) 1 gain ( g , v ) ( 1 ) F ( g ) (( 1 ) F ( h )) + + = − ⋅ + − ⋅ � out out h IMP ∈ – Both Both g g and and h h stand for gates stand for gates – – IMP IMP is the set of gates whose is the set of gates whose ouputs ouputs are implied by the are implied by the – assignment assignment � Gain is the global effect of one assignment within its Gain is the global effect of one assignment within its � implication range implication range

4000 3524 3500 3406 3000 2668 2644 2500 2207 Estimation(Pi) Imax/Fanout 2000 1799 Imax/Gain 1545 1527 1500 1366 1292 1000 882 872 688 650 524 517 500 228 214 223 210 0 C432 C499 C880 C1355 C1908 C2670 C3540 C5315 C6288 C7552 Circuits

Runtime(sec) Circuit Imax/Fanout Imax/Gain C432 0.08 0.12 C499 0.15 0.24 C880 0.22 0.3 C1355 0.37 0.93 C1908 0.53 1.48 C2670 2.02 1.87 C3540 1.63 6.23 C5315 4.72 4.48 C6288 3.48 6.13 C7552 9.25 9.63

Switch Current vs Power-on Current 4000 (-0.90%) 3556 3524 3500 2911 3000 (+4.38%) 2668 2556 2500 (-24.18%) 2207 Estimation(Pi) Max Pow er-up Current 2000 Max Sw itching Current (+14.70%) 1545 (+17.66%) 1500 1366 1347 1161 (-1.76%) 898 882 1000 (+86.96%) 688 (+35.05%) 524 368 388 500 (+16.33%) (+21.86%) 228 223 196 183 0 C432 C499 C880 C1355 C1908 C2670 C3540 C5315 C6288 C7552 Circuits

� Power Gating may lead to more severe reliability Power Gating may lead to more severe reliability � problem problem � Maximum Current Estimation Considering Power Maximum Current Estimation Considering Power � Gating should be used to guide P/G wires planning and Gating should be used to guide P/G wires planning and optimization optimization