Distributed, virtual and real debugging of a MIPS SoC Martin - PowerPoint PPT Presentation

Distributed, virtual and real debugging of a MIPS SoC Martin Strubel section5.ch Distributed, virtual and real debugging of a MIPS SoC Martin Strubel section5.ch 02/2013

Distributed, Flight plan virtual and real debugging of a MIPS SoC Martin Strubel section5.ch 1 Debugging a complex FPGA design (in theory) ❼ A SoC (System on Chip) example ❼ MAIS : A portable MIPS soft core by Ren´ e Doss ❼ The Test Access Port (TAP): A generic debug interface 2 Virtualizing the hardware ❼ ’Model in the loop’ techniques ❼ Making real software speak to virtual hardware 3 Demos ❼ Debugging the virtual chip ❼ Debugging the real hardware

Distributed, The challenge virtual and real debugging of a MIPS Debug this: SoC Martin Strubel section5.ch Figure: Somewhat unreadable schematic

Distributed, Divide et impera virtual and real debugging of a MIPS SoC Martin Strubel section5.ch Figure: Simplified SoC schematic with Debug port

❼ Distributed, Existing solutions virtual and real debugging of a MIPS SoC Proprietary solutions from various FPGA vendors: Martin Strubel section5.ch Signal inspection tool Soft CPU core Vendor ChipScope microblaze Xilinx Reveal mico32 Lattice SignalTap NiosII Altera Table: Tool examples ❼ Virtualization capabilities depend on second party simulation tools ( ✩✩✩ - ✩✩✩✩✩ ) ❼ Debug port itself can sometimes not be simulated

Distributed, Existing solutions virtual and real debugging of a MIPS SoC Proprietary solutions from various FPGA vendors: Martin Strubel section5.ch Signal inspection tool Soft CPU core Vendor ChipScope microblaze Xilinx Reveal mico32 Lattice SignalTap NiosII Altera Table: Tool examples ❼ Virtualization capabilities depend on second party simulation tools ( ✩✩✩ - ✩✩✩✩✩ ) ❼ Debug port itself can sometimes not be simulated ❼ No easy DIY virtualization of the hardware due to proprietary and closed libraries.

❼ ❼ ❼ Distributed, The MIPS-compatible MAIS CPU virtual and real debugging of a MIPS SoC Martin Strubel Introducing a soft cpu core may speed up proto- section5.ch typing/debugging. (exercised previously with ZPU soft core) Why MIPS? ❼ Well-established architecture with many derivatives (Loongson SoC, Router chipsets) ❼ Fast, easy to implement, resource saving ❼ Actively maintained tool chain and emulators

Distributed, The MIPS-compatible MAIS CPU virtual and real debugging of a MIPS SoC Martin Strubel Introducing a soft cpu core may speed up proto- section5.ch typing/debugging. (exercised previously with ZPU soft core) Why MIPS? ❼ Well-established architecture with many derivatives (Loongson SoC, Router chipsets) ❼ Fast, easy to implement, resource saving ❼ Actively maintained tool chain and emulators ❼ MAIS design by Ren´ e Doß: ❼ Well-portable MIPS 32 bit implementation ❼ Access to VHDL sources

Distributed, In Circuit Emulation (ICE) virtual and real debugging of a MIPS SoC Martin Strubel section5.ch In emulation mode, the CPU... ❼ takes opcodes from the EMUIR register ❼ executes them when it gets an emuexec pulse ❼ exchanges data with the debugger via the EMUDATA register

Distributed, In Circuit Emulation (ICE) virtual and real debugging of a MIPS SoC Martin Strubel section5.ch In emulation mode, the CPU... ❼ takes opcodes from the EMUIR register ❼ executes them when it gets an emuexec pulse ❼ exchanges data with the debugger via the EMUDATA register Full remote control of the CPU via a test access port (TAP)!

Distributed, Debugger components virtual and real debugging of a MIPS SoC Martin Strubel section5.ch 1 The developer’s front end: The GNU debugger ( gdb ) Figure: GDB Debugger connects to back end via a TCP remote debugging protocol. Means: Distributed across networks!

Distributed, Debugger components virtual and real debugging of a MIPS SoC Martin Strubel section5.ch 1 The developer’s front end: The GNU debugger ( gdb ) 2 The back ends: 1 uniproxy : a JTAG debug server 2 qemu : a MIPS CPU emulator Figure: GDB and uniproxy Debugger connects to back end via a TCP remote debugging protocol. Means: Distributed across networks!

Distributed, Debugger components virtual and real debugging of a MIPS SoC Martin Strubel section5.ch 1 The developer’s front end: The GNU debugger ( gdb ) 2 The back ends: 1 uniproxy : a JTAG debug server 2 qemu : a MIPS CPU emulator 3 JTAG debugger hardware: USB JTAG adapter Figure: ICEbear JTAG adapter Debugger connects to back end via a TCP remote debugging protocol. Means: Distributed across networks!

❼ ❼ ❼ Distributed, Virtualize the hardware virtual and real debugging of a MIPS SoC Martin Strubel section5.ch ❼ qemu: software-emulated MIPS CPU – a functional model ❼ Write C code to functionally emulate attached hardware

Distributed, Virtualize the hardware virtual and real debugging of a MIPS SoC Martin Strubel section5.ch ❼ qemu: software-emulated MIPS CPU – a functional model ❼ Write C code to functionally emulate attached hardware ❼ VHDL simulation: cycle accurate – a timing model ❼ Typically: Simulation of logical behaviour ❼ Somewhat precise waveform output

❼ ❼ Distributed, Virtualize the hardware virtual and real debugging of a MIPS SoC Martin Strubel section5.ch ❼ VHDL simulation: cycle accurate – a timing model ❼ Typically: Simulation of logical behaviour ❼ Somewhat precise waveform output Figure: Timing accurate simulation

Distributed, Make ants meet virtual and real debugging of a MIPS SoC Make antz meet... Martin Strubel section5.ch Drawing by Britta Schneider

Distributed, Now seriously: make ends meet virtual and real debugging of a MIPS Task: Make real world software speak to virtual hardware. SoC Martin Strubel section5.ch Result: ghdlex OpenSource simulator extension library: ❼ Describe virtual board in XML − → ❼ Attach virtual components in HDL design: ❼ JTAG debugger ❼ shared RAM ❼ USB FIFO ❼ I/O pins, registers Figure: XML hardware description

Distributed, Virtual Hardware virtual and real debugging of a MIPS SoC Virtual Hardware Client/Driver Software Martin Strubel section5.ch GNU debugger ghdlex library User program netpp.vpi Virtual pins Virtual RAM Virtual hardware Virtual driver JTAG debugger VHDL-Simulation, unit under test netpp client JTAG processor Virtual (VHDL) USB-FIFO

Distributed, Virtual Hardware virtual and real debugging of a MIPS SoC Virtual Hardware Client/Driver Software Martin Strubel section5.ch GNU debugger ghdlex library User program netpp.vpi Virtual pins Virtual RAM Virtual hardware Virtual driver JTAG debugger VHDL-Simulation, unit under test netpp client JTAG processor Virtual (VHDL) USB-FIFO Expose design components to the network!

Distributed, Distributed processing virtual and real debugging of a MIPS SoC JTAG Martin Strubel section5.ch Embedded device Camera (Data acquisition) Windows PC, Driver software Developer, Debugger front end Simulation ghdlex speaks netpp (network property protocol), therefore things can run anywhere. ❼ HDL-Simulation on powerful main frame ❼ Data routing from real world software on Windows PC to simulation ❼ Debugger (Laptop) connecting to any of the debug servers

❼ ❼ ❼ ❼ ❼ ❼ ❼ Distributed, Now, where’s the bug? virtual and real debugging of a MIPS SoC Martin Strubel section5.ch ❼ Bug could sit: ❼ .. in peripheral access (HDL design), or the CPU ❼ .. in SoC firmware (Code running on CPU core) ❼ .. in host (PC) software

❼ ❼ ❼ ❼ ❼ Distributed, Now, where’s the bug? virtual and real debugging of a MIPS SoC Martin Strubel section5.ch ❼ Bug could sit: ❼ .. in peripheral access (HDL design), or the CPU ❼ .. in SoC firmware (Code running on CPU core) ❼ .. in host (PC) software ❼ .. in Debugger components itself (reserve many gaelic curses) ❼ .. between two human ears

Distributed, Now, where’s the bug? virtual and real debugging of a MIPS SoC Martin Strubel section5.ch ❼ Bug could sit: ❼ .. in peripheral access (HDL design), or the CPU ❼ .. in SoC firmware (Code running on CPU core) ❼ .. in host (PC) software ❼ .. in Debugger components itself (reserve many gaelic curses) ❼ .. between two human ears ❼ Avoid to introduce bugs during development: ❼ Verify CPU behaviour against qemu (functional simulation) ❼ Keep device configuration in exactly one XML file ❼ Use Makefile rules or similar to keep source and generated files in sync ( → GNU make ) ❼ Introduce detection mechanisms: ID codes or functionality descriptors (JTAG USERCODE register)

Distributed, Hands on! virtual and real debugging of a MIPS SoC Martin Strubel section5.ch Demos: 1 Debugging the simulation 2 Debugging the hardware: HDR-60 FPGA camera kit 3 Verifying the CPU using qemu

Distributed, Hardware Test Bench virtual and real debugging of a MIPS SoC Martin Strubel section5.ch 32 bit instruction bus 32 bit CPU core SMMU Core Event Controller 32 bit bus L1 instr L1 cache L1 data L1 data Bank A Bank B Bank A/B Bank C DMA Controller FliX DSP MUX JPEG encoder FIFO FPGA USB 16 bit DMA FIFO isochronous (FX2) Control bus (MMR) USB EP (in) Figure: JPEG encoder test bench