Motivation Hilbert Transform Implementation Results Digital Hilbert Transformers for FPGA-based Phase-Locked Loops Martin Kumm, M. Shahab Sanjari Gesellschaft f¨ ur Schwerionenforschung mbH Department of Synchrotron Radio Frequency Darmstadt, Germany September 9, 2008 Martin Kumm, M. Shahab Sanjari Digital Hilbert Transformers for FPGA-based PLLs
Motivation Hilbert Transform Implementation Results Content Motivation 1 Hilbert Transform 2 Implementation 3 Results 4 Martin Kumm, M. Shahab Sanjari Digital Hilbert Transformers for FPGA-based PLLs
Motivation Controlling the phase in accelerating cavities Hilbert Transform Phase-locked loop Implementation Phase detection Results The Problem: Phase detection in a particle accelerator The Problem A 180 ◦ phase difference is necessary for acceleration Accelerating cavities drift in phase ➯ Using active control ➯ Exact phase measurement needed Frequency is varying during acceleration (0.8...5.4 MHz) Martin Kumm, M. Shahab Sanjari Digital Hilbert Transformers for FPGA-based PLLs
Motivation Controlling the phase in accelerating cavities Hilbert Transform Phase-locked loop Implementation Phase detection Results Phase-locked loop (PLL) Location of the PLL A frequency change to a constant intermediate frequency (IF) is necessary A tracked offset local oscillator (LO) is needed This is done with an “all-digital” phase-locked loop within an FPGA A “direct digital synthesizer” (DDS) is used for signal generation ➯ Main challenge: phase detection (PD) Martin Kumm, M. Shahab Sanjari Digital Hilbert Transformers for FPGA-based PLLs
Motivation Controlling the phase in accelerating cavities Hilbert Transform Phase-locked loop Implementation Phase detection Results Phase detection with a real signal The Problem We have: s ( n ) = ˆ u cos(Ω n + φ 0 ) (Ω = 2 π f / f s ) We want: ϕ ( n ) = Ω n + φ 0 The direct way: ϕ ( n ) = 1 u arccos( s ( n )) ˆ � not unique for all amplitudes � amplitude dependent � better: using Hilbert transform Martin Kumm, M. Shahab Sanjari Digital Hilbert Transformers for FPGA-based PLLs
Motivation Controlling the phase in accelerating cavities Hilbert Transform Phase-locked loop Implementation Phase detection Results Phase detection with an analytic signal Extending s ( n ) with an imaginary component H{ s ( n ) } results in s ( n ) = s ( n ) + j H{ s ( n ) } ue j (Ω n + φ 0 ) = ˆ u [cos(Ω n + φ 0 ) + j sin(Ω n + φ 0 )] = ˆ We obtain the so called “analytic signal” Then: ϕ ( n ) = arctan( Im { s ( n ) } Re { s ( n ) } ) � Efficient FPGA computation possible with CORDIC Algorithm ➯ How to build an analytic signal? Martin Kumm, M. Shahab Sanjari Digital Hilbert Transformers for FPGA-based PLLs
Motivation Hilbert Transform Hilbert Transform Principle Implementation Architectures for the Hilbert Transform Results Hilbert Transform Principle The Hilbert transform can be defined using a convolution: H{ s ( n ) } = s ( n ) ⊛ h H ( n ) ➯ It can be seen as a digital filter with a transfer function j for − π < Ω < 0 H H ( e j Ω ) = 0 for Ω = 0 − j for 0 < Ω < π The magnitude response is unity (exept for Ω = 0) The phase response is +90 ◦ for positive and − 90 ◦ for negative frequencies The analytic signal s ( n ) + j H{ s ( n ) } has no signal components for negative frequencies Martin Kumm, M. Shahab Sanjari Digital Hilbert Transformers for FPGA-based PLLs
Motivation Hilbert Transform Hilbert Transform Principle Implementation Architectures for the Hilbert Transform Results Architectures for the Hilbert Transform Possible architectures 1 90 ◦ phase splitting network ➯ Special case: FIR filter for imaginary part 2 Complex filter Martin Kumm, M. Shahab Sanjari Digital Hilbert Transformers for FPGA-based PLLs
Motivation Hilbert Transform Hilbert Transform Principle Implementation Architectures for the Hilbert Transform Results Architectures for the Hilbert Transform Possible architectures 1 90 ◦ phase splitting network ➯ Special case: FIR filter for imaginary part 2 Complex filter Martin Kumm, M. Shahab Sanjari Digital Hilbert Transformers for FPGA-based PLLs
Motivation FIR Implementation Hilbert Transform Consequences of the amplitude error Implementation Frequency Sampling Filter Results FIR Implementation - Structure of the Filter FIR Implementation Impulse response has 0.8 0.6 an odd symmetry and 1 0.4 all even coefficients are zero 2 0.2 ➯ Fast and efficient h H (n) 0 implementation possible −0.2 −0.4 ➯ An 11-Tap FIR filter was −0.6 implemented −0.8 −6 −4 −2 0 2 4 6 n Martin Kumm, M. Shahab Sanjari Digital Hilbert Transformers for FPGA-based PLLs
Motivation FIR Implementation Hilbert Transform Consequences of the amplitude error Implementation Frequency Sampling Filter Results FIR Implementation - Magnitude and Phase Response 5 150 0 100 arg H H (e j ω ) 50 |H H (e j ω )| −5 0 −10 −50 −100 −15 −150 −20 −0.5 0 0.5 −0.5 0 0.5 f/f s f/f s Figure: Magnitude Response Figure: Phase Response ➯ The amplitude response is an approximation to 0 dB ➯ The phase response is exactly ± 90 ◦ Martin Kumm, M. Shahab Sanjari Digital Hilbert Transformers for FPGA-based PLLs
Motivation FIR Implementation Hilbert Transform Consequences of the amplitude error Implementation Frequency Sampling Filter Results FIR Implementation - Consequences of the amplitude error The gain of the imaginary path of the total filter is varying ... ... while the real part of the filter ( z − D ) is constant ➯ The vector in the complex plane forms an ellipse rather than a circle ➯ This causes a dynamic phase error, which can be analytically determined from the amplitude gain error ( G e ) to be maximal � 1+ G e ; (∆ ϕ = ϕ ′ − ϕ ) ∆ ϕ max ( G e ) = π G e 2 − 2 arcsin Martin Kumm, M. Shahab Sanjari Digital Hilbert Transformers for FPGA-based PLLs
Motivation FIR Implementation Hilbert Transform Consequences of the amplitude error Implementation Frequency Sampling Filter Results FIR Implementation - Total Phase and Phase Error 1 150 100 0.5 (arg x , −arg x)/ ∆ϕ max 50 arg x , [ ° ] 0 0 −50 G e =1 G e =1 −0.5 −100 G e =0.707 G e =0.707 G e =0.1 G e =0.1 −150 −1 −300 −200 −100 0 100 200 300 −300 −200 −100 0 100 200 300 φ [ ° ] φ [ ° ] Figure: Total Phase Figure: Phase Error ➯ Mean error is zero, base frequency is twice the signal frequency ➯ Phase error can be cancelled by filtering (PLL loop bandwidth ≪ signal frequency) Martin Kumm, M. Shahab Sanjari Digital Hilbert Transformers for FPGA-based PLLs
Motivation FIR Implementation Hilbert Transform Consequences of the amplitude error Implementation Frequency Sampling Filter Results FIR Implementation - Filter for Cancelling the Phase Error Transforming an continous 1 low-pass filter F LP ( s ) = 1+ sT c to a discrete filter leads to b 0 F LP ( z ) = 1+ a 1 z − 1 (rectangle method ) Defining b 0 := 2 − M results in a 1 = 2 − M − 1 ➯ no multipliers needed, efficient FPGA implementation possible fs Cut-off frequency is f c = 2 M − 1 Martin Kumm, M. Shahab Sanjari Digital Hilbert Transformers for FPGA-based PLLs
Motivation FIR Implementation Hilbert Transform Consequences of the amplitude error Implementation Frequency Sampling Filter Results FIR Implementation - Frequency response of low-pass filter 0 −20 |F LP (e j ω )| [dB] −40 −60 N=1 N=3 −80 N=4 N=8 −100 −3 −2 −1 0 10 10 10 10 f/f s Using N filters in series improves the attenuation Martin Kumm, M. Shahab Sanjari Digital Hilbert Transformers for FPGA-based PLLs
Motivation FIR Implementation Hilbert Transform Consequences of the amplitude error Implementation Frequency Sampling Filter Results Architectures for the Hilbert Transform Possible architectures 1 90 ◦ phase splitting network ➯ Special case: FIR filter for imaginary part 2 Complex filter Martin Kumm, M. Shahab Sanjari Digital Hilbert Transformers for FPGA-based PLLs
Motivation FIR Implementation Hilbert Transform Consequences of the amplitude error Implementation Frequency Sampling Filter Results Frequency Sampling Filter (FSF) - Idea FSF Idea FSF are a generalization of “cascaded integrator comb” (CIC) filters Usually used as decimation filter (see e.g. Meyer-Baese, Digital Signal Processing with Field Programmable Gate Arrays , Springer, 2007) Idea: A basic comb filter of the form F ( z ) = 1 − z − N c produces zeros at multiple angles of Ω = 360 ◦ N c Additional IIR pole filters are chosen to cancel undesired zeros Using simple coefficients from the set {− 1 , 0 , 1 } results in hardware efficient filters Martin Kumm, M. Shahab Sanjari Digital Hilbert Transformers for FPGA-based PLLs
Motivation FIR Implementation Hilbert Transform Consequences of the amplitude error Implementation Frequency Sampling Filter Results Frequency Sampling Filter (FSF) - Example (1) 10 0 −10 −20 −30 −40 0 100 200 300 Ω [ ° ] 40 30 20 10 0 −10 −20 0 100 200 300 Ω [ ° ] Martin Kumm, M. Shahab Sanjari Digital Hilbert Transformers for FPGA-based PLLs
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