STRS Waveform Porting for NASA’s CoNNeCT Project December 2, 2011 Dale Mortensen
Outline CoNNeCT project overview The Ported Waveform – TDRSS application “What is all this STRS stuff, anyhow?” Development approach Porting metrics & results Does STRS really make a difference? 2
CoNNeCT Project Overview Communications, Navigation, and Networking reConfigurable Testbed a.k.a. “Space Communications and Networking (SCAN) Testbed ” International Space Station(ISS) Exterior Payload, scheduled to launch in 2012 Investigating the application of SDRs to NASA Missions SDR technology development Validating future mission operational capabilities First flight for STRS 3
CoNNeCT Flight Payload 4
JPL Baseline Waveform Description Transmit Receive Description (return link) (forward link) BPSK Modulation Direct Sequence Spread Spectrum (PN Short code) Spreading (with bypass option for DG2) Data Group 1, Mode 2 TDRSS Data Group 2, non-coherent functionality ½ rate convolutional ½ rate Viterbi decoding Forward Error encoding Correction 24 kbps (spread ), 18 kbps (spread ), User Data Rates 192, 769 kbps (non-spread) 155, 769 kbps (non-spread) IESS-308, V.35 Scrambling NRZ-M Data Formatting 5
Space Telecommunications Radio System Hardware Interface Definition Common APIs Radio Platform GPM (GPP) User Data HID Standard Interface Interface STRS OE for FPGA WF App. SPM (FPGA) WF App. (from PIM) STRS API Platform Specific Wrapper HAL WF Control: HAL Modulator WF App. (from PIM) Data HID Encoder WF STRS STRS API Modulator Format HAL Control HAL HAL CLK Converter WF HAL HID Control Carrier HAL RFM Synthesizer HID Data Conversion/ Sampling Hardware Abstraction Layer 6 6
Development Approach GSFC GRC Waveform STRS TDRSS Reference OE Development on Firmware COTS SDR STRS Heritage Reference WF Port to JPL SDR TDRSS STRS Performance (prototype) Compliance Testing Testing Flight SDR JPL BPM Prototype STRS Compliant OE Documentation: HID, CoNNeCT SDR Development Dev Guide, Test WF 7
Porting to Target Platform COTS SDR JPL SDR VxWorks OS change RTEMS Sampling Rate change 80 MHz <80 MHz ADC < 14-bit 14-bit DAC Xilinx Xilinx Xilinx Xilinx ½ FPGA Size XQR2V Xilinx XC2V6000 XQR2V Xilinx XC2V6000 3000 XC2V6000 3000 XC2V6000 Configuration GRC OE JPL OE File Format Format Format FPGA STRS Proprietary Wrapper TTL SpaceWire Data Interface Clk & Data RFM Ø Carrier Freq. setting S-band RF Ø AGC no RF Module Module HW temperature Ø Control compensation
Processor Code porting - SLOC 5000 Estimate 4500 Device Driver WF Class 850 4000 S ource L ines O f C ode 3500 3000 2500 846 2000 3500 3690 1500 1000 2346 500 0 Estimate (3500) GGT SDR3000 (4540) Initial Ported JPL Prototype (3192)
FPGA Utilization Initial Ported FPGA Resource Utilization Utilization Total Slice Registers 94.5 % 59.8 % 4 input LUTs 90.0 % 70.4 % occupied Slices 176.7 % 99.9 % Slices containing only related logic 176.7 % 94.1 % Slices containing unrelated logic 0 % 5.9 % 4 input LUTs 98.2 % 72.4 % MULT18X18s 109.4 % 85.4 % *porting of the waveform involved reducing the functionality of the original GSFC waveform so as to fit into the smaller JPL SDR FPGAs. There was also a speed reduction constraint. 10
Porting Effort Overview • 374 working (8 hour) days total effort divided between 3 engineers • total calendar time 2 years • tools used/required: Matlab/Simulink, Synplicity HDL synthesis (now Synopsis) , Xilinx ISE, RTEMS development tools, Prototype BPM • Does not include CoNNeCT System integration, performance, and environmental testing (vibe, thermal vacuum, EMI) • NOTE: Porting effort blurs with system integration and flight platform specific functions. The COTS platform did not have an RF front end. 11
Porting Effort Breakdown Porting Effort breakdown other preparation 2% (tools, etc.) 3% testing 5% reviews 6% OE Integration & documentation WF Control SW 6% 20% Test procedures (writing) 9% Platform specific additions Porting FPGA 11% TDRSS Core 35% Almost half of the porting core WF effort was not related to enhancements waveform reuse 3% 12
STRS Effects Porting Effort breakdown How did the WF port benefit with STRS? OE Integration & WF Control SW 20% 1. Software for control was recompiled for new target processor, because of standard APIs. 2. Commanding and configuring from OE was the same, because of standard APIs. The OE integration & WF Control slice would have been significantly larger. 13
Conclusions Porting from more capable platform can be difficult: 1. Waveform design may need to change (e.g. analog I/Q mod instead of digital) Reduction in features/performance. SDR Platform should compensate for all temperature effects with OE 2. and/or dedicated HW. However, some effects are waveform dependent. STRS Architecture was helpful for this development: 3. despite the COTS to space-based platform disparity the standard APIs reduced porting effort. Allowed for some parallel development, (forced by schedule constraints) Better metrics could be found in a comparison of COTS to JPL 4. Prototype, or a port of the current waveform on the JPL Flight SDR to another STRS flight SDR. 14
Contact Information Dale J. Mortensen ASRC Aerospace Corp. @ NASA Glenn Research Center 216-433-6698 dale.mortensen@nasa.gov http://spaceflightsystems.grc.nasa.gov/SpaceOps/CoNNeCT/ 15
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