CPE 335 CPE 335 Computer Organization MIPS ISA Dr. Iyad Jafar Adapted from Dr. Gheith Abandah Slides http://www.abandah.com/gheith/Courses/CPE335_S08/index.html CPE 232 MIPS ISA 1
(vonNeumann) Processor Organization Control needs to � CPU Memory Devices input instructions from Memory 1. Control Control Input Input issue signals to control the 2. Datapath information flow between the Output Datapath components and to Datapath components and to control what operations they perform Fetch control instruction sequencing 3. � Datapath needs to have the Exec Decode � components – the functional units and storage (e.g., register file) needed to execute instructions � interconnects - components connected so that the instructions can be accomplished and so that data can be loaded from and stored to Memory y CPE 232 MIPS ISA 2
Computer Language In order to command the computer, we must speak its � language, i.e. we must know its instructions and programming model (Instruction Set Architecture) model (Instruction Set Architecture) Computer instructions are represented as binary electric � signals at the hardware level Programming by storing signals at the hardware level. Programming by storing instructions in their binary format (Machine Language) is tedious and time consuming. Assembly language came into action and represented � machine codes/instructions as words. Assembling was done initially by hand Later assemblers were introduced initially by hand. Later, assemblers were introduced. In assembly, programmers have to write one line of code for � each instruction The programmers have to think like a each instruction. The programmers have to think like a machine. High-level programming languages and compilers High level programming languages and compilers � � CPE 232 MIPS ISA 3
4 Computer Language CPE 232 MIPS ISA
RISC - Reduced Instruction Set Computer � RISC philosophy � fixed instruction lengths � load-store instruction sets � limited addressing modes � limited operations � limited operations � MIPS, Sun SPARC, HP PA-RISC, IBM PowerPC, HP (Compaq) Alpha (Compaq) Alpha, … � Instruction sets are measured by how well compilers use them as opposed to how well assembly language use them as opposed to how well assembly language programmers use them Design goals: speed, cost (design, fabrication, test, packaging), size, power consumption, reliability, memor space (embedded s stems) memory space (embedded systems) CPE 232 MIPS ISA 5
MIPS R3000 Instruction Set Architecture (ISA) Registers � Instruction Categories � Computational p R0 R0 - R31 R31 � Load/Store � Jump and Branch � Floating Point - coprocessor PC HI HI � Memory Management Memory Management LO � Special 3 Instruction Formats: all 32 bits wide OP rs rd sa funct R format rt I format OP rs rt immediate OP OP J format J format jump target CPE 232 MIPS ISA 6
Review: Unsigned Binary Representation Hex Binary Decimal 0x00000000 0…0000 0 0x00000001 0…0001 1 2 31 2 30 2 29 . . . 2 3 2 2 2 1 2 0 bit weight 0x00000002 0…0010 2 31 30 29 . . . 3 2 1 0 bit position 0x00000003 0x00000003 0 0…0011 0011 3 3 1 1 1 . . . 1 1 1 1 bit 0x00000004 0…0100 4 0x00000005 0…0101 5 0x00000006 0…0110 6 1 0 0 0 . . . 0 0 0 0 - 1 0x00000007 0…0111 7 0x00000008 0x00000008 0…1000 0…1000 8 8 0x00000009 0…1001 9 2 32 - 1 … 2 32 - 4 0xFFFFFFFC 1…1100 2 32 - 3 0xFFFFFFFD 1…1101 2 32 - 2 0xFFFFFFFE 1…1110 2 2 2 32 - 1 0xFFFFFFFF 1…1111 CPE 232 MIPS ISA 7
Aside: Beyond Numbers � American Std Code for Info Interchange (ASCII): 8-bit bytes representing characters ASCII ASCII Ch Char ASCII ASCII Ch Char ASCII ASCII Ch Char ASCII ASCII Ch Char ASCII ASCII Ch Char ASCII ASCII Ch Char 0 Null 32 space 48 0 64 @ 96 ` 112 p 1 33 ! 49 1 65 A 97 a 113 q 2 2 34 34 “ 50 50 2 2 66 66 B B 98 98 b b 114 114 r r 3 35 # 51 3 67 C 99 c 115 s 4 EOT 36 $ 52 4 68 D 100 d 116 t 5 5 37 37 % % 53 53 5 5 69 69 E E 101 101 e e 117 117 u u 6 ACK 38 & 54 6 70 F 102 f 118 v 7 39 ‘ 55 7 71 G 103 g 119 w 8 8 bksp bksp 40 40 ( ( 56 56 8 8 72 72 H H 104 104 h h 120 120 x x 9 tab 41 ) 57 9 73 I 105 i 121 y 10 LF 42 * 58 : 74 J 106 j 122 z 11 11 43 43 + + 59 59 ; ; 75 75 K K 107 107 k k 123 123 { { 12 FF 44 , 60 < 76 L 108 l 124 | 15 5 47 / / 63 63 ? 79 9 O O 111 o o 127 DEL CPE 232 MIPS ISA 8
MIPS Register File Register File Register File � Holds thirty-two 32-bit registers 32 bits 5 � Two read ports and 32 src1 addr src1 data � One write port 5 src2 addr 32 locations 5 dst addr ds add � Registers are 32 src2 32 write data data � Faster than main memory - But register files with more locations B t i t fil ith l ti write control are slower (e.g., a 64 word file could be as much as 50% slower than a 32 word file) - Read/write port increase impacts speed quadratically R d/ it t i i t d d ti ll � Easier for a compiler to use - e.g., (A*B) – (C*D) – (E*F) can do multiplies in any order vs. e.g., (A B) (C D) (E F) can do multiplies in any order vs. stack � Can hold variables so that - code density improves (since register are named with fewer bits d d it i ( i i t d ith f bit than a memory location) CPE 232 MIPS ISA 9
Aside: MIPS Register Convention Name Register Usage Preserve Number on call? $zero 0 constant 0 (hardware) n.a. $at 1 reserved for assembler n.a. $v0 - $v1 2-3 returned values no $a0 - $a3 4-7 arguments yes $t0 - $t7 8-15 temporaries no $s0 - $s7 16-23 saved values yes $t8 - $t9 24-25 temporaries no $gp 28 global pointer yes $sp 29 stack pointer yes $fp 30 frame pointer yes $ra 31 return addr (hardware) yes CPE 232 MIPS ISA 10
MIPS Arithmetic Instructions � MIPS assembly language arithmetic statement add add $t0, $s1, $s2 $t0, $s1, $s2 sub $t0, $s1, $s2 � Each arithmetic instruction performs only one � Each arithmetic instruction performs only one operation operation � Each arithmetic instruction fits in 32 bits and specifies � Each arithmetic instruction fits in 32 bits and specifies exactly three operands exactly three operands y y p p destination ← source1 op destination ← source1 op source2 source2 � Operand order is fixed (destination first) � Operand order is fixed (destination first) � Those operands are all contained in the datapath’s register file ( $t0 $ 1 $ 2 ) register file ( $t0,$s1,$s2 ) – indicated by $ indicated by $ CPE 232 MIPS ISA 11
Assembly Example 1 � Given the following piece of C code, find the equivalent assembly code using the basic MIPS ISA given so far. a = b – c d = 3 * a d = 3 a Solution: assume that the variables a, b, c, and d are associated with registers $s0 $s1 $s2 and $s3 associated with registers $s0, $s1, $s2, and $s3, respectively, by the compiler. sub $s0, $s1, $s2 # $s0 contains b – c b $ 0 $ 1 $ 2 # $ 0 t i b add $s3, $s0 ,$s0 # $s3 contains 2*a add $s3, $s3, $s0 # $s3 contains 3*a CPE 232 MIPS ISA 12
Assembly Example 2 � Given the following piece of C code, find the equivalent assembly code using the basic MIPS ISA given so far. f = (g + h) – (i + j) Solution: assume that the variables f g h i and j are Solution: assume that the variables f, g, h, i, and j are associated with registers $s0, $s1, $s2, $s3, and $s4, respectively, by the compiler. add $t0, $s1, $s2 # $t0 contains g + h add $t1, $s3 ,$s4 # $t1 contains i + j dd $t1 $ 3 $ 4 # $t1 t i i + j sub $s0, $t0, $t1 # $s0 contains (g+h) – (i+j) CPE 232 MIPS ISA 13
Machine Language - Add Instruction � Instructions are 32 bits long � Arithmetic Instruction Format (R format): � Arithmetic Instruction Format (R format): add $t0, $s1, $s2 op rs rt rd t d shamt funct h t f t op 6-bits opcode that specifies the operation rs 5-bits register file address of the first source operand rt 5-bits register file address of the second source operand rd 5-bits register file address of the result’s destination shamt 5-bits shift amount (for shift instructions) funct 6-bits function code augmenting the opcode CPE 232 MIPS ISA 14
Machine language – Arithmetic Example 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits Op code rs rt rd shamt funct � Machine code for add $s0, $t0, $s0 in hexadecimal op = 0x0 rs = $t0 = 0x08 rt = $s0 = 0x10 0 0 $ 0 0 08 $ 0 0 10 rd = $s0 = 0x10 shamt = 0x00 funct = 0x20 000000 01000 10000 10000 00000 100000 � Machine code for sub $s0, $t0, $s0 in hexadecimal M hi d f b $ 0 $t0 $ 0 i h d i l op = 0x0 rs = $t0 = 0x08 rt = $s0 = 0x10 rd = $s0 = 0x10 shamt = 0x00 funct = 0x22 000000 01000 10000 10000 00000 100010 CPE 232 MIPS ISA 15
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