ABCD: Booleanizing Continuous Systems for Analog/Mixed-Signal - PowerPoint PPT Presentation

ABCD: Booleanizing Continuous Systems for Analog/Mixed-Signal Design, Simulation, and Verification Aadithya V. Karthik, Sayak Ray, Pierluigi Nuzzo, Alan Mishchenko, Robert Brayton, and Jaijeet Roychowdhury EECS Dept., The University of California, Berkeley TAU 2014, Santa Cruz Aadithya V. Karthik (aadithya@berkeley.edu) Mar 2014, TAU, Santa Cruz 1/19

The Problem: AMS Verification Example: SERDES PLL Analog parts CDR I/O Surrounded by Digital Logic • Want to verify complete system >1V – e.g., eye opening height > 1V? • Proof or counter-example needed Aadithya V. Karthik (aadithya@berkeley.edu) Mar 2014, TAU, Santa Cruz 2/19

Our approach: “Booleanize” the analog parts Challenge: ABCD: Boolean Analog models + Digital models (don't mix) (don't mix) approximation ALL Continuous Boolean BOOLEAN Best verification tools = all Boolean, no continuous SAR-ADC Boolean T/H Boolean approximation comparator approximation Boolean DAC approximation Analog components Digital components Verification tools accept Fast Formal verification, high-speed simulation, test pattern generation, ... … for the full combined system! Aadithya V. Karthik (aadithya@berkeley.edu) Mar 2014, TAU, Santa Cruz 3/19

ABCD: Boolean, but Accurate • What is “accurate Booleanization”? disc. o/p 110 Boolean disc. Logic i/p 010 discretized ckt. signals disc. time Boolean state More bits, better accuracy Aadithya V. Karthik (aadithya@berkeley.edu) Mar 2014, TAU, Santa Cruz 4/19

Prior work: ABCD-L (DAC 2013) ABCD-L Linear Analog Purely Boolean Linear Circuit Model Works only for linear systems! Example: Channel + Equalizer Linearize Bit Sequence Aadithya V. Karthik (aadithya@berkeley.edu) Mar 2014, TAU, Santa Cruz 5/19

Introducing ABCD-NL ABCD-NL Non-Linear Purely Boolean Analog Circuit Model Rest of this talk How ABCD-NL works 1 Results: Charge pump, ADC, DAC, etc. 2 End user applications 3 High-speed simulation, formal verification, test pattern generation, etc. for non-linear AMS ckts. Aadithya V. Karthik (aadithya@berkeley.edu) Mar 2014, TAU, Santa Cruz 6/19

ABCD-NL Models are FSMs ABCD-NL Non-Linear Purely Boolean FSM Analog Circuit Model • Finite number of states • Arcs denoting state transitions – Each arc: ip/op pair • Purely Boolean form 1100 0010 Aadithya V. Karthik (aadithya@berkeley.edu) Mar 2014, TAU, Santa Cruz 7/19

Key idea: DC, TRAN FSM states DC Non-Linear Eventually settles 1 Analog Circuit and never changes 0 TRAN (DC input → DC output) Starts at DC0 and eventually settles at DC1 1 • DC FSM states w/ loops • Multiple such DC states – Capture different DCOPs • DCOPs don't change instantly • TRAN FSM states – Between each pair of DC states • Purely Boolean Model Aadithya V. Karthik (aadithya@berkeley.edu) Mar 2014, TAU, Santa Cruz 8/19

Booleanizing a Charge Pump (1/3) Discretize Vup, Vdown using Do SPICE simulations 1 1 bit each, Vout using 5 bits UP low DOWN high UP high DOWN low Active Exactly 1 high at any time Both high Both low Dormant Aadithya V. Karthik (aadithya@berkeley.edu) Mar 2014, TAU, Santa Cruz 9/19

Booleanizing a Charge Pump (2/3) Analyze SPICE waveforms 2 Build “Analog Transition Table” TRAN path DC3 to DC2: up (down) goes 1→0 (0→1) Total time 20.63ns, o/p starts @ 31, becomes 30 @ 213.6ps, …. Aadithya V. Karthik (aadithya@berkeley.edu) Mar 2014, TAU, Santa Cruz 10/19

Booleanizing a Charge Pump (3/3) Analog Transition Table → Boolean Model 3 disc. o/p Combinational disc. Logic i/p Registers <ipbv> <cstbv> <opbv> <nstbv> disc. Boolean state time • i/p: 2-bit encoding • o/p: 5-bit encoding – 32 levels in [0, Vdd] • FSM state: 19 bits – Lots of don't cares (75%) Aadithya V. Karthik (aadithya@berkeley.edu) Mar 2014, TAU, Santa Cruz 11/19

ABCD-NL: The 3-Step Algorithm Do SPICE simulations 1 Analyze SPICE waveforms 2 Build “Analog Transition Table” Analog Transition Table → Boolean Model 3 Aadithya V. Karthik (aadithya@berkeley.edu) Mar 2014, TAU, Santa Cruz 12/19

Simulating the Boolean Model i/p waveform Discretize into FSM symbols Simulate FSM (Fast, Table-lookup) Map back to analog Aadithya V. Karthik (aadithya@berkeley.edu) Mar 2014, TAU, Santa Cruz 13/19

Charge Pump: Long PRBS Non-linear analog dynamics accurately captured over long time-frame ~10x Speedup, even in Python Aadithya V. Karthik (aadithya@berkeley.edu) Mar 2014, TAU, Santa Cruz 14/19

Circuits Successfully Booleanized Delay line Charge pump Power grid Equalizer I/O signaling system SAR-ADC Aadithya V. Karthik (aadithya@berkeley.edu) Mar 2014, TAU, Santa Cruz 15/19

AMS Verification: The Flow AMS System to Property to be Proof or Counter be verified verified example “Booleanize” Boolean Model (manually) via ABCD-NL ABC Safety vs Liveness “Booleanize” (manually) Input Constraints Aadithya V. Karthik (aadithya@berkeley.edu) Mar 2014, TAU, Santa Cruz 16/19

Example: Verifying a Signaling System What is the max bitrate that can be sustained? Ans: 2.56Gbps ABCD model ABC Specification verification engine (Bob Brayton's group) Aadithya V. Karthik (aadithya@berkeley.edu) Mar 2014, TAU, Santa Cruz 17/19

Summary • AMS modelling, verification a challenge: 20% bugs • Our approach: Booleanize AMS Components – ABCD-L: for linear AMS systems – ABCD-NL: for non-linear systems • Applied to A/D and D/A converters, delay lines, charge pumps, equalizers, filters, on-chip power grids, etc. • Accurate and Scalable • Applications – High-speed simulation – Formal verification (in conjunction with ABC) Aadithya V. Karthik (aadithya@berkeley.edu) Mar 2014, TAU, Santa Cruz 18/19

Questions Aadithya V. Karthik (aadithya@berkeley.edu) Mar 2014, TAU, Santa Cruz 19/19