A Highly Integrated 65-nm SoC Process with Enhanced - PowerPoint PPT Presentation

A Highly Integrated 65-nm SoC Process with Enhanced Power/Performance of Digital and Analog Circuits L. T. Clark, D. Zhao, T. Bakhishev, H. Ahn, E. Boling, M. Duane, K. Fujita*, P. Gregory, T. Hoffmann, M. Hori*, D. Kanai*, D. Kidd, S. Lee, Y. Liu, J. Mitani*, J. Nagayama*, S. Pradhan, P. Ranade, R. Rogenmoser, L. Scudder, L. Shifren, Y. Torii*, M. Wojko, Y. Asada*, T. Ema*, and S. Thompson SuVolta, Inc. *Fujitsu Semiconductor Ltd 1

Presentation Outline • Low-power SoC platform • Process and device results • Circuit results – SRAM V DDmin reduction – Digital logic power reduction – Analog matching and performance • Conclusions 2

Low-Power SoC Platform Transistor level benefits Higher drive current • ARM M-0 Tighter V T control 200MHz @ 0.6V • Seamless integration to baseline • - V DDmin ~400mV - Lower I SB - 4X R out Product level benefits - 2x better AVT V DD reduction from 1.2V to 0.9V • Nearly half power and matched delay – Extended voltage range • Improved low voltage yield – • Significantly extends 65/55-nm node life with enhanced functionality • Lower cost alternative to 40-nm migration 3

Presentation Outline • Low-power SoC platform • Process and device results • Circuit results – SRAM V DDmin reduction – Digital logic power reduction – Analog matching and performance • Conclusions 4

Deeply Depleted Channel (DDC) • 65-nm example transistor • Seamless integration into baseline process • Legacy devices supported – Legacy IP support possible 5

DDC Matching Benefits • Improved transistor matching – Un-doped channel • Better RDF – Epitaxial channel formed after wells • No well proximity effects – Excellent V T Control – No halo implants • Further improves RDF • No halo proximity effects • Epi layer thickness control – Wafer: 1 σ = 0.25% – Overall 1 σ = 0.65% 26.9 Thickness (nm) 27.3 6

DDC I EFF Increase 60 • Better SCE – Thinner t OX 50 DDC I EFF gain (%) – DIBL reduced 40 ~50mV/V – Higher low V DD 30 mobility 20 • I EFF w/ same 10 – L E – I OFF 0 0.6 0.7 0.8 0.9 1.0 1.1 1.2 V DD (V) 7

Threshold Voltage Control • Enables better systematic corners Logic Device SRAM 0.70 Control Control 0.65 0.50 NMOS V T (V) NMOS V T (V) 3 σ 0.60 1 σ 2 σ 0.45 0.55 0.50 0.40 DDC DDC 0.45 -0.50 -0.45 -0.40 -0.35 0.3 0.4 0.5 0.6 0.7 PMOS V T (V) PMOS V T (V) 8

SRAM Transistor Matching • Better SRAM matching: Lower SRAM V DDmin • DDC σ σ σ σ ∆ V T invariant across V T range 50 50 40 40 0.5 (mV) 0.5 (mV) 30 30 ~40% ~60% σ∆ Vt/2 20 σ∆ Vt/2 20 σ∆ σ∆ σ∆ σ∆ σ∆ σ∆ 10 10 0 0 -0.55 -0.47 -0.39 0.36 0.40 0.44 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 V T (V) V T (V) 9

Junction Leakage • I junction well controlled, consistent across V T range µ m) µ m) PMOS leakage (pA/um) (L = 1 µ µ µ NMOS leakage (pA/um) (L = 1 µ µ µ 100 100 10 10 1 1 0.30 0.35 0.40 0.45 0.50 -0.2 -0.3 -0.4 -0.5 V T (V) V T (V) 10

DDC Enhanced Body Effect 300 Control DDC 250 Body factor (mV/V) FF 200 150 I off TT 100 50 SS 0 NMOS PMOS NMOS PMOS I ON SRAM Logic • Highly doped screen layer increases body coefficient by ~4x to ~7x • Allows significant process corner pull-in 11

Corner Pull-in in Action NMOS PMOS 12

Presentation Outline • Low-power SoC platform • Process and device results • Circuit results – SRAM V DDmin reduction – Digital logic power reduction – Analog matching and performance • Conclusions 13

SRAM V DDmin Improvement • No circuit changes from baseline—same masks – 6-T 9.4Mb arrays 100 – No redundancy 90 80 % Yield (9.4 Mb) 70 60 50 40 30 20 -40C 10 RT 125C 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 V DD (V) 14

Circuit Logic Corner Pull-in • Inverter ring oscillator measurements 0.45 • Baseline V DD = 1.2V Control 0.40 DDC SS • DDC V DD = 0.9V DDC TT 0.35 Total power (mW) DDC FF • SS frequency 0.30 400MHz to 150MHz 0.25 by adjusting BB 0.20 FF@ • FF frequency Vbb=-0.8V 0.15 500MHz to 200MHz 0.10 by adjusting BB SS@ 0.05 Vbb=0V 0.00 100 200 300 400 500 600 Frequency (MHz) 15

No Body Effect Stack Penalty • Higher low V DS I EFF counteracts body bias 1.0 NAND DDC impact in stacks (normalized to inverter) 0.9 NOR DDC Relative RO Frequency NAND Control 0.8 NOR Control • Ring oscillator 0.7 – NAND (NMOS stack) NOR (PMOS stack) 0.6 gates are faster than 0.5 baseline 0.4 0.3 • DDC V DD = 0.9V 0.2 • Control V DD = 1.2V 2 3 4 Number of Inputs 16

Logic Power Reduction with DDC • Inverter ring oscillator 0.6 • Sweep V DD and reverse body bias 0.5 Total power (mW) 0.4 • 38% greater 38% 0.3 performance at same total power 0.2 47% 0.1 • 47% less power at 0.0 same performance 0 200 400 600 Frequency (MHz) 17

Logic Power Reduction with DDC • Large logic/SRAM embedded block Normalized Power dissipation • 5.8M gates Dynamic 1.0 Static • 1.45Mb SRAM 0.8 • Same mask set 0.6 0.4 • 47% less power at same performance 0.2 – Control V DD = 1.2V 0.0 – DDC V DD = 0.9V Control DDC with Vbb V DD = 1.2V V DD = 0.9V 18

ARM M-0 Core Results • Preliminary results – DDC implementation achieves 200 MHz @ V DD = 0.6V • Body bias selection not optimized 19

Presentation Outline • Low-power SoC platform • Process and device results • Circuit results – SRAM V DDmin reduction – Digital logic power reduction – Analog matching and performance • Conclusions 20

DDC Analog Benefits • Higher I EFF DDC 7.0 Control 6.0 NMOS I DS (mA) • Reduced V Dsat 5.0 4.0 • Higher R DS 3.0 2.0 • Improved 1.0 matching 0.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 V DS (V) 21

DDC Analog Circuit Improvement • Current mirrors • Matching improved by – Local: 40% NMOS, 30% PMOS – 16x current gain – Global: 40% NMOS, 30% PMOS 22

DDC Analog Circuit Improvement • Differential Amplifier 1.2 Control DC measurements DDC 1.0 Output voltage (V) – DDC V DD = 1.2V and 0.8 Control V DD = 0.9V 0.6 0.4 0.2 0.0 -20 -10 0 10 20 Input offset (mV) 23

DDC Analog Circuit Improvement • OTA DC measurements • Gain improved 12dB – More consistent gain – Same layout • Better matching allows smaller analog circuits – Reduced loading – Better slew rate 24

Presentation Outline • Low-power SoC platform • Process and device results • Circuit results – SRAM V DDmin reduction – Digital logic power reduction – Analog matching and performance • Conclusions 25

Conclusions • DDC 65/55-nm SOC process – Nominal V DD scaled to 0.9V from 1.2V—up to 47% power savings – Proven on large logic/memory blocks – ARM M-0 core operates at 200 MHz at V DD = 0.6V • 6-T SRAM V DDmin below 400mV demonstrated on 9.4Mb arrays – Un-doped channel mitigates RDF – No halo, well proximity effects • Enhanced body effect – Allows effective logic corner pull-in with body biasing • Improved analog circuit matching and gain • Processing compatible with multi-V T and legacy devices – Straightforward support for existing IP 26

Thank You for Your Attention • Questions? 27