A commercial platform for wireless handsets Charles F Sturman VP - PowerPoint PPT Presentation

Software Defined Modem A commercial platform for wireless handsets Charles F Sturman VP Marketing June 22 nd ~ 24 th Brussels charles.stuman@cognovo.com www.cognovo.com

Agenda  SDM – Separating hardware from software  Why now  Multimode modem processing requirements  A whole system approach  Optimising processor resources for the task in hand  Low power design and scalability  Performance benchmarks achieved  Software development methodology  Task scheduling and mapping  System design, verification and optimisation  Bottom up vs Top down  Modem Compute Engine  A commercially available platform for low-power handheld wireless 2

Why Now ?  A changing market  Rapid evolution in applications and services  Many products need wireless : Smartphones, Tablets, Gaming, Home entertainment 500  Rapidly increasing modem complexity LTE-A 1Gbps 450 300GOp/s 400  350 Driven by applications and services Bitrate, Mbps 300  250 Increasing time to market and cost LTE 200 50GOp/s 150 HSPA+ 100 20GOp/s GPRS HSPA 50 200MOp/s 5GOp/s GSM 0  SDM delivers 1990 1995 2000 2005 2010 2015  Faster : Time to market and market response  Flexibility : One chip = many products / many standards  Smaller : Smaller die size = Lower cost 3

Modem Requirements Layer 3 Radio Resource Control Protocol Stack Layer 2 Radio Link Control and Media Access Control Layer 1 Real-time control software PHY Control Sub-frame Sequencing Time-critical sequencing Modem & Channel Codec Hard-real-time signal processing  Layer 1 combines real-time control with time critical signal processing 4

Modem Requirements CPHY PHY Message Interface Message Interface Layer 3 Radio Resource Control Radio Layer 1 Control State Machine Layer 1 Control State Machine Layer 2 Driver Radio Link Control and Media Access Control Sub-frame Sub-frame Sub-frame Sub-frame Sub-frame Layer 1 Control Control Sequences Sequences Sequences PHY Control Traditionally, custom Sub-frame Sequencing RF IC Timing Timing Timing ASIC hardware Modem & Channel Codec Signal Processing Signal Processing Signal Processing  Layer 1 combines real-time control with time critical signal processing  Deterministic operation has traditionally demanded hardware  SDM enables the entire modem to be expressed in software 5

Modem Requirements CPHY PHY Message Interface Message Interface Radio Layer 1 Control State Machine Layer 1 Control State Machine Driver Sub-frame Sub-frame Sub-frame Sub-frame Sub-frame Control Control Sequences Sequences Sequences S/w implementation hosted on heterogeneous RF IC Timing Timing Timing processor platform Signal Processing Signal Processing Signal Processing Modem Compute Engine  Layer 1 combines real-time control with time critical signal processing  Deterministic operation has traditionally demanded hardware  SDM enables the entire modem to be expressed in software 6

A System Solution for SDM – Layer 1 Partitioning Applications Hardware abstraction & API Protocol Plane Control Plane Data Plane Common services Modem Physical Layer 1 Layers 2, 3, 4 specific Layer Protocol Common functions operation Stack Code re-use Libraries SDM-OS Software Hardware Heterogeneous Multi-processing Modem Compute Engine Generic s/w Protocol execution Processor Control Sequence Data environment System Processor Processor Processor Common Infrastructure The Soft Modem RF External Software Domain 7

Layer 1 Logical Layer 1 RF PHY Control Driver Layer 1 Partitioning PHY Sequences Layer 1 Control  GP processor support for Layer 1 control PHY Kernels PHY PHY Task Sequencing  Real-time deterministic task sequencing driven by on-air timing Hard-real-time Signal Processing  PPA efficient wireless algorithmic processing  No modem-specific hardware processing Modem Compute Engine Logical Control Sequence Data Layer 1 PHY PHY Processor Processor Processor PHY Sequences Kernels Control Common Infrastructure The Soft Modem RF External Software Domain 8

Layer 1 System Design  Existing Layer 1 design & implementation must be supported  Seamless integration with existing protocol stacks  Operational control, management & service provision  Largely specific to SDM platform : Auto generated code avoids creating extra engineering workload & human error  Sub-frame sequencing  Extension of present PHY modelling carried out with e.g. Simulink or Co-Ware : Graphical catpure and auto-compilation of flow control Logical Layer 1 PHY PHY PHY Sequences Kernels Control  Uplink / Downlink PHY algorithms  Compilation of existing fixed-point C-code, with efficient profiling and optimisation tools. Must be able to re-validate against reference models 9

Introducing Cognovo’s Modem Compute Engine (MCE) Real-time L1 / PHY computing system Modem Compute Engine VSP Sub-system  TCM VSP Sub-system PHY Data Plane ARM VSP Sub-system Datapath DBG Datapath DBG CPU Datapath DBG Datapath DBG  CACHE Register bank Register bank Multi-core Vector Signal Processing Datapath DBG Datapath DBG Ardbeg VSP Ardbeg VSP Register bank Register bank VLIW Controller CTL VLIW Controller CTL Ardbeg VSP Ardbeg VSP Register bank Register bank SDM VLIW Controller CTL VLIW Controller CTL  Ardbeg VSP Ardbeg VSP I-TCM D-TCM I-TCM D-TCM Designed-for-Wireless ISA Sequencer VLIW Controller CTL VLIW Controller CTL Bridge I-TCM D-TCM I-TCM D-TCM Bus Interface Unit Bus Interface Unit I-TCM D-TCM I-TCM D-TCM  Bus Interface Unit Bus Interface Unit Instruction & Data parallelism Bus Interface Unit Multilayer Vector Interconnect Bus Interface Unit Interrupt Multilayer Vector Interconnect Ctl  Timing >> 130 GOp/s @500 MHz Multilayer Vector Interconnect VDMA Shared Memory and Slow System VDMA Shared Memory Clock Unit RAM VDMA Shared Memory  11-way VLIW Peripheral – APB Bus Power Control System – AXI Bus Control 32b Bridge  32-way complex vector data-path FEC Watchdog HARQ RF IF Memory Engine Data 128b Bridge Timers  Layer 1 Control Plane ARM JTAG System Coresight DMA VSP Trace  ARM CPU hosts SDM OS and Layer 1  Mode independent timing / power ctl Dual VSP Core (MCE120)  Multi-standard Turbo engine  Cat 4 LTE capable (150Mb DL / 50Mb UL)  RF interface  Simultaneous DL and UL: 62% loaded at 400MHz  7.5 mm 2 and < 100mw in 32nm SDM Sequencer   Precise scheduling of kernels  Similar power consumption to existing  Autonomous operation removes baseband silicon but with smaller area overhead from L1 CPU 10

MCE120 Performance Benchmarks @ 40nm LP 350 R8 LTE-FDD Configurations 300  5MHz Channel Cat 2 : 5-40 Mbps 250  10 MHz Channel Cat 3 : 5-80 Mbps Clock Frequency, MHz  20 MHz Channel Cat 4 : 20-150 Mbps 200 R5 to R8 3G HSPA Configurations 150  R5 W-CDMA : 384 Kbps  R6 HSPA : 14 Mbps 100  R7 HSPA+ MIMO : 28 Mbps 50  R8 HSPA+ Dual Carrier : 42 Mbps 0 Connectivity 0 20 40 60 80 100 120 140 160  WiFi 802.11g : 54 Mbps On-air Bit-rate, Mbps  DVB-T (HD) : 15 Mbps MCE clock frequency vs on-air bit-rate  Combined DL / UL estimates for 3GPP Rel5 to Rel8  HSPA evolution and LTE : Clock-rate scaling from 75MHz to 300MHz  Clock rate and power can also scale with signal conditions  High SNR (light signal processing) to low SNR (heavy signal processing) 11 11

Power & Performance Scalability  The same architecture will scale up 500 LTE-A 1Gbps 450 300GOp/s 400 or down 350 Bitrate, Mbps 300 250 LTE 200 50GOp/s 150 HSPA+ Higher clock rate 100 20GOp/s GPRS HSPA 50 200MOp/s 5GOp/s GSM More memory 0 Modem Compute Engine 1990 1995 2000 2005 2010 2015 More processing resources: TCM ARM VSP Sub-system CPU CACHE Multi-core / Multi-way Datapath DBG Datapath DBG Register bank Register bank Ardbeg VSP Ardbeg VSP Sequencer VLIW Controller CTL VLIW Controller CTL Bridge I-TCM D-TCM I-TCM D-TCM Bus Interface Unit Bus Interface Unit Interrupt Ctl Timing Multilayer Vector Interconnect and Slow System Clock Unit RAM VDMA Shared Memory Peripheral – APB Bus Power Control System – AXI Bus Control 32b Bridge Watchdog HARQ Turbo RF IF Memory Bridge Data 128b Timers ARM JTAG System Lower clock rate Coresight DMA VSP Trace Less memory Less processing resources: Multi-core / Multi-way  Modem requirements drive Power Performance and Area  PPA drives silicon implementation and process choice 12

A System Solution for SDM – Development Partitioning Applications Protocol Plane Control Plane Data Plane Design Modem Environment Physical Layer 1 Layers 2, 3, 4 specific Layer System Protocol System operation Stack integration & PHY Kernel SDK SDM-OS modelling Library Software Hardware Modem Compute Engine Kernel PHY coding & Generic s/w Protocol SDK optimisation execution Processor Control Sequence Data environment System Processor Processor Processor Common Infrastructure The Soft Modem RF External Software Domain 13