A 83-dB SFDR 10-MHz Bandwidth A 83-dB SFDR 10-MHz Bandwidth - PowerPoint PPT Presentation

A 83-dB SFDR 10-MHz Bandwidth A 83-dB SFDR 10-MHz Bandwidth Continuous-Time Delta-Sigma Modulator Employing a One-Element- M d l t E l i O El t Shifting Dynamic Element Matching Hong Phuc Ninh, Masaya Miyahara, and Akira Matsuzawa Akira Matsuzawa Tokyo Institute of Technology, Japan Matsuzawa Matsuzawa & Okada Lab. & Okada Lab.

1 Outline • Background Background • Proposed one-element-shifting (OES) DEM method (OES) DEM method • Implementation and measurement results lt • Conclusion Matsuzawa Matsuzawa 2011/11/30 H.P. Ninh, Tokyo Tech. & Okada Lab. & Okada Lab.

2 Outline • Background Background • Proposed one-element-shifting (OES) DEM method (OES) DEM method • Implementation and measurement results lt • Conclusion Matsuzawa Matsuzawa 2011/11/30 H.P. Ninh, Tokyo Tech. & Okada Lab. & Okada Lab.

3 Receiver architecture TV tuner 2G/3G cellular WLAN … *10 MHz bandwidth (our target design) *High Dynamic Range (DR) *High Spurious-Free Dynamic Range (SFDR) ΣΔ ADC is a hopeful solution to achieve high DR & SFDR Matsuzawa Matsuzawa 2011/11/30 H.P. Ninh, Tokyo Tech. & Okada Lab. & Okada Lab.

ΣΔ ADC architecture 4 N: Quantizer resolution N: Quantizer resolution OSR: oversampling ratio (=Fs/2/BW) L: filter order L=4 L=4 150 Continuous-time ΣΔ ADC with N=1,2,3,4 of F s multi-bit quantizer & DAC L=3 ation o 100 Our design L=2 DAC linearity SNR L=1 L=1 S Limita is an issue i i 50 Low resolution L 0 1 10 100 OSR Matsuzawa Matsuzawa 2011/11/30 H.P. Ninh, Tokyo Tech. & Okada Lab. & Okada Lab.

5 Linearity issues of feedback DAC Input stage of ΣΔ ADC f ΣΔ ADC C in C i I t t Unity cell R in N V ip V om + - V V im - + V op P R in Static error Static error C in in Mismatch In n <7> In p <7> In n < 1 > In p < 1 > In n < 0 > In p < 0 > Ex: Ex: 1.05 1 05 1 02 1.02 0 98 0.98 Mismatch deviation Transitor size For simplicity, a 3bit DAC is considered Matsuzawa Matsuzawa 2011/11/30 H.P. Ninh, Tokyo Tech. & Okada Lab. & Okada Lab.

6 Linearity issues of feedback DAC Input stage of ΣΔ ADC f ΣΔ ADC C in C i I t t R in N V ip V om + - V im V - + V op P R in Dynamic error Dynamic error C in in Glitch In n <7> In p <7> In n < 1 > In p < 1 > In n < 0 > In p < 0 > Parasitic capacitance P iti it Normalized Non-ideal switching glitch energy For high speed operation, dynamic F hi h d ti d i error becomes more critical Matsuzawa Matsuzawa 2011/11/30 H.P. Ninh, Tokyo Tech. & Okada Lab. & Okada Lab.

7 What is glitch energy? Switching asymmetry I (uA) T (ns) Glitch energy (Glitch area) Glitch energy: average of 8192points Matsuzawa Matsuzawa 2011/11/30 H.P. Ninh, Tokyo Tech. & Okada Lab. & Okada Lab.

8 Requirements of DAC linearity Static error Dynamic error Mismatch Glitch 90 80 70 60 60 50 0.3% 1.6% 40 40 0 1 2 3 4 5 R Requirement for SNR>70dB i t f SNR 70dB (BW=10MHz, Fs=500MHz) Matsuzawa Matsuzawa 2011/11/30 H.P. Ninh, Tokyo Tech. & Okada Lab. & Okada Lab.

9 Outline • Motivation Motivation • Proposed one-element-shifting (OES) DEM method (OES) DEM method • Implementation and measurement results lt • Conclusion Matsuzawa Matsuzawa 2011/11/30 H.P. Ninh, Tokyo Tech. & Okada Lab. & Okada Lab.

10 DEM topology summary DWA-group TC-group Prop. (ADWA, Bi-DWA) (RTC, RSTC) OES Glitch Bad Excellent Good Mismatch Good Mismatch Good Excellent Excellent Bad Bad (DEM: to improve DAC linearity) *Data Weighted Averaging (DWA) [1] *Advanced Random DWA (ADWA) [2] *Bi-directional DWA (Bi-DWA) [3] *Thermometer Coding (TC, w/o DEM) *Th t C di (TC / DEM) *Randomized Thermometer Coding (RTC) [4] *Restricted Swapping Thermometer Coding (RSTC) [5] [1] R. T. Baird et al. , IEEE Trans. Circuits Syst. II, , Dec. 1995. [1] R T Baird et al Dec 1995 IEEE Trans Circuits Syst II [2] I. Fujimori et al. , IEEE J. Solid-State Circuits , Dec. 2000. [3] D. H. Lee et al. , IEEE Trans. Circuits Syst. II, Oct. 2007. [4] D. H. Lee et al. , IEEE Trans. Circuits Syst. II, Feb. 2009. Matsuzawa Matsuzawa 2011/11/30 H.P. Ninh, Tokyo Tech. [5] M. H. Shen et al. , IEEE Trans. Circuits Syst. II, May. 2010. & Okada Lab. & Okada Lab.

11 OES: Eliminating Effect of Glitch By reducing the number of switched elements g ( n ) (w/ same other glitch conditions) g ( n ) Glitch energy + − + − ≤ + − − ≥ − ⎧ ⎧ 2 ( ) ( 1 ), ( ) ( 1 ) x ( n ) x ( n 1 ), x ( n ) x ( n 1 ) N x n x n x n x n = = ⎨ ⎨ ( ) g n g ( n ) − − − + − > − − < − ⎩ ⎩ ( ) ( 1 ) , ( ) ( 1 ) 2 N x ( n ) x ( n 1 ), x ( n ) x ( n 1 ) N x n x n x n x n = − − g ( n ) x ( n ) x ( n 1 ) Matsuzawa Matsuzawa 2011/11/30 H.P. Ninh, Tokyo Tech. & Okada Lab. & Okada Lab.

12 Glitch Energy g ( n ) Glitch energy Sim condition *tfb tf trb tr 20ps *tfb-tf = trb-tr =20ps *Cp=10fF *3bit DAC ( (w/o mismatch) ) Requirement for SNR>70dB (BW=10MHz, Fs=500MHz) Matsuzawa Matsuzawa 2011/11/30 H.P. Ninh, Tokyo Tech. & Okada Lab. & Okada Lab.

13 OES: Preserve Reduction of Mismatch Effect By reducing the mismatch error spectrum in the interesting bandwidth (w/ same mismatch deviation) (w/ same mismatch deviation) OES ADWA RSTC (Good) (Good) (Excellent) (Excellent) (Bad) (Bad) pectrum [dB] pectrum [dB] pectrum [dB] 0 0 -20 -20 -40 -40 AC mismatch sp AC mismatch sp AC mismatch sp -60 -60 -80 -80 -100 -100 -120 120 -120 120 DA DA DA 0 50 100 150 200 250 0 50 100 150 200 250 Frequency [MHz] Frequency [MHz] (1%mismatch input: 1MHz@ 30dBFS) (1%mismatch, input: 1MHz@-30dBFS) Matsuzawa Matsuzawa 2011/11/30 H.P. Ninh, Tokyo Tech. & Okada Lab. & Okada Lab.

14 Mismatch requirement Mismatch DAC area Sim condition Mismatch Mismatch *tfb tf trb tr 0ps *tfb-tf = trb-tr =0ps *Cp=10fF Relaxation *3bit DAC (w/o glitch) ( g ) Requirement for SNR>70dB (BW=10MHz, Fs=500MHz) Matsuzawa Matsuzawa 2011/11/30 H.P. Ninh, Tokyo Tech. & Okada Lab. & Okada Lab.

15 With Both of Glitch and Mismatch 90 w/glitch w/o DEM w/glitch OES 80 RSTC RTC 70 60 Bi-DWA ADWA 50 50 0 1 2 3 mismatch OES achieves better SNDR & SFDR OES achieves better SNDR & SFDR performance over the published DEM methods Sim condition Sim condition *tfb-tf = trb-tr =20ps *Cp=10fF *3bit DAC (w/ mismatch) Matsuzawa Matsuzawa 2011/11/30 H.P. Ninh, Tokyo Tech. & Okada Lab. & Okada Lab.

16 Outline • Background Background • Proposed one-element-shifting (OES) DEM method (OES) DEM method • Implementation and measurement results lt • Conclusion Matsuzawa Matsuzawa 2011/11/30 H.P. Ninh, Tokyo Tech. & Okada Lab. & Okada Lab.

17 System architecture M d l t Modulator Spec S FF+FB, 3 rd order 4bit AD/DA BW: 10MHz Fs: 500MHz Fs: 500MHz SNDR req : 70dB 90nm CMOS process Matsuzawa Matsuzawa 2011/11/30 H.P. Ninh, Tokyo Tech. & Okada Lab. & Okada Lab.

18 OES DEM architecture Example for 4 elements DAC OES DEM OES DEM *Simplicity (no extra pointer, no register) i t i t ) *Relax timing requirement for feedback DAC f f db k DAC Matsuzawa Matsuzawa 2011/11/30 H.P. Ninh, Tokyo Tech. & Okada Lab. & Okada Lab.

19 Modulator layout OES DEM Core area: 9% Power consumption: 6% Matsuzawa Matsuzawa 2011/11/30 H.P. Ninh, Tokyo Tech. & Okada Lab. & Okada Lab.

20 Measurement Results Remove by w/o DEM digital filter g OES DEM OES-DEM BW W/o DEM OES DEM SNDR 62.8 63.3 SFDR 71.8 82.6 Matsuzawa Matsuzawa 2011/11/30 H.P. Ninh, Tokyo Tech. & Okada Lab. & Okada Lab.

21 Measurement Results SNDR-w/o DEM SFDR-w/o DEM SNDR-OES DEM SFDR-OES DEM Average of 10dB SFDR improvement are achieved Matsuzawa Matsuzawa 2011/11/30 H.P. Ninh, Tokyo Tech. & Okada Lab. & Okada Lab.

22 Performance Comparison Unit Unit This work This work [6] [6] [7] 7] [8] [8] Type/ DEM pe/ DEM CT/OES T/OES CT/DW T/DWA DT/DEM T/DEM CT/DW T/DWA B Ban B andwidth d idth d idth MHz MH MH MH 10 10 10 10 20 20 20 20 5 5 10 10 10 10 Samp. freq. Samp. freq. MHz Hz 500 500 640 640 80 80 300 300 SFDR SFDR dB dB 83 83 77 77 * 85 85 64 64 * SNDR SNDR dB dB 65 65 63.9 63.9 75.4 75.4 62.5 62.5 DR DR dB dB 66 66 68 68 - 70.2 70.2 P Power ower mW W 15 15 7 15.7 15 58 58 58 58 36 36 36 36 5 31 5 3 5.31 31 CMOS proc. CMOS proc. nm 90 130 130 180 180 110 FoM FoM fJ/conv J/conv 530 530 1130 130 750 750 240 240 *Better SFDR (compared with conv. DEM method) *Less power (w/ same SFDR) Less power (w/ same SFDR) [6]J. G. Jo et al. , ASSCC Dig. Tech. Papers , Nov. 2010. [7]O. Rajaee et al. , IEEE J. Solid-State Circuits , Apr. 2010. Matsuzawa Matsuzawa 2011/11/30 [8]K. Matsukawa et al. , IEEE Symp. on VLSI Circuits , Jun. 2009. H.P. Ninh, Tokyo Tech. & Okada Lab. & Okada Lab.