A 61.5dB SNDR Pipelined ADC Using Simple Highly-Scalable Ring - PowerPoint PPT Presentation

A 61.5dB SNDR Pipelined ADC Using Simple Highly-Scalable Ring Amplifiers Benjamin Hershberg 1 , Skyler Weaver 1 , Kazuki Sobue 2 , Seiji Takeuchi 2 , Koichi Hamashita 2 , Un-Ku Moon 1 1 Oregon State University, Corvallis, OR, USA 2 Asahi Kasei Microdevices, Atsugi, Japan

An Incomplete Solution • Goal: develop truly scalable amplifiers – Conventional opamps are fundamentally ill-suited for nanoscale CMOS – Efficiency in amplification-based designs is actually getting worse • ADCs – Amplifier-less ADCs (i.e. SARs) provide excellent scalability for some of the design space – Scalable amplifiers are needed to cover the entire ADC design space • The more scalable options we have, the better 2

Beating the Trend A scalable amplifier must • Operate well in nanoscale CMOS • Improve with nanoscale CMOS Circuit level requirements • Minimize SNR loss from low-voltage, degrading r o • Exploit digital scaling benefits • Avoid conventional RC-based settling 3

Beating the Trend - V DZ V OUT V IN + Ring Amplifier (Ringamp, RAMP) 4

Ring Amplification Basic Theory

Ring Amplifier: Basic Theory RST Example MDAC V CMO Feedback Structure RST V IN AMP ±V REF RST C LOAD V CMX • Basic MDAC test structure 6

Ring Amplifier: Basic Theory RST Example MDAC V CMO Feedback Structure RST RST V IN V OUT V IN ±V REF RST C LOAD V CMX =0.6V • Ring Oscillator • Unstable… …but will oscillate around the correct settled value 7

Ring Oscillator Sample Waveform 1.2 1.2 1 1 V IN V CMX = 0.6V (ideal settled input value) 0.8 0.8 Volts Volts 0.6 0.6 0.4 0.4 0.2 0.2 0 0 0 1 2 3 4 5 6 0 1 2 3 4 5 6 time (ns) time (ns) 8

Ring Amplifier: Basic Theory RST Example MDAC V CMO Feedback Structure -V OS + RST RST RST - V IN V DZ ±V REF + RST RST C LOAD +V OS - V CMX • Split signal into two separate paths • Embed offset in each path 9

Ring Amplifier Sample Waveform V DZ = 0mV 1.2 1.2 1 1 0.8 0.8 Volts Volts 0.6 0.6 0.4 0.4 V AP V BP 0.2 0.2 - V IN V OUT 0 0 V DZ V A 0 1 2 3 4 5 6 0 1 2 3 4 5 6 + time (ns) time (ns) V BN V AN 10

Ring Amplifier Sample Waveform V DZ = 0mV 1.2 1.2 1 1 0.8 0.8 Volts Volts 0.6 0.6 0.4 0.4 V AP V BP 0.2 0.2 - V IN V OUT 0 0 V DZ V A 0 1 2 3 4 5 6 0 1 2 3 4 5 6 + time (ns) time (ns) V BN V AN 11

Ring Amplifier Sample Waveform V DZ = 0mV 1.2 1.2 1 1 0.8 0.8 Volts Volts 0.6 0.6 0.4 0.4 V AP V BP 0.2 0.2 - V IN V OUT 0 0 V DZ V A 0 1 2 3 4 5 6 0 1 2 3 4 5 6 + time (ns) time (ns) V BN V AN 12

Ring Amplifier Sample Waveform V DZ = 0mV 1.2 1.2 1 1 0.8 0.8 Volts Volts 0.6 0.6 0.4 0.4 V AP V BP 0.2 0.2 - V IN V OUT 0 0 V DZ V A 0 1 2 3 4 5 6 0 1 2 3 4 5 6 + time (ns) time (ns) V BN V AN 13

Ring Amplifier Sample Waveform V DZ = 200mV 1.2 1.2 1 1 0.8 0.8 Volts Volts 0.6 0.6 0.4 0.4 0.2 0.2 0 0 0 1 2 3 4 5 6 0 1 2 3 4 5 6 time (ns) time (ns) Plateaus form at dead-zone crossings 14

Ring Amplifier Sample Waveform V DZ = 250mV 1.2 1.2 1 1 0.8 0.8 Volts Volts 0.6 0.6 0.4 0.4 0.2 0.2 0 0 0 1 2 3 4 5 6 0 1 2 3 4 5 6 time (ns) time (ns) 15

Ring Amplifier Sample Waveform V DZ = 300mV 1.2 1.2 1 1 0.8 0.8 Volts Volts 0.6 0.6 0.4 0.4 0.2 0.2 0 0 0 1 2 3 4 5 6 0 1 2 3 4 5 6 time (ns) time (ns) 16

Ring Amplifier Sample Waveform V DZ = 350mV 1.2 1.2 1 1 0.8 0.8 Volts Volts 0.6 0.6 0.4 0.4 0.2 0.2 0 0 0 1 2 3 4 5 6 0 1 2 3 4 5 6 time (ns) time (ns) 17

Ring Amplifier Sample Waveform V DZ = 400mV 1.2 1.2 1 1 0.8 0.8 Volts Volts 0.6 0.6 0.4 0.4 0.2 0.2 0 0 0 1 2 3 4 5 6 0 1 2 3 4 5 6 time (ns) time (ns) 18

Ring Amplifier Sample Waveform V DZ = 250mV 1.2 1.2 1 1 0.8 0.8 Volts Volts 0.6 0.6 0.4 0.4 0.2 0.2 0 0 0 1 2 3 4 5 6 0 1 2 3 4 5 6 time (ns) time (ns) Decreasing V OV reduces slew-rate 19

V OV Dynamic Pinch-off A V2 *(V IN *A V1 + V OS ) A V2 +V OS - - V IN V OUT V DZ + A V1 -V OS + A V2 *(V IN *A V1 - V OS ) 20

V OV Dynamic Pinch-off A V2 *(V IN *A V1 + V OS ) A V2 +V OS - - V IN V OUT V DZ + A V1 -V OS + – I D decreases • V OV → I D 2 A V2 *(V IN *A V1 - V OS ) – R o increases • Dominant pole → DC 21

Dynamic Dead-zone Adjustment A V1 I P - V IN I P -I N V DZ + I N • Initial: A V1 limited by slewing • Final: A V1 set by AC small-signal • Dynamically adjusts input-referred dead-zone • Enhances Speed / Accuracy trade-off 22

Core Benefits

Ring Amplifier Core Benefits Slew-based charging • Charges with maximally biased, digitally-switched current sources – Can be very small, even for large C LOAD – Decouples internal speed vs. output load requirements 24

Ring Amplifier Core Benefits Scalability (Speed/Power) • Internal speed/power (mostly) independent of C LOAD – Inverter t d , crowbar current, parasitic C’s – Digital power-delay product scaling benefits apply • Captures the same power/speed trends as digital circuits V DD I AVG D OUT D IN t d C GS PDP = V DD ·I AVG ·t d = E tot 25

Ring Amplifier Core Benefits Scalability (Output Swing / SNR) • Compression immune: rail-to-rail output swing • 50dB: Input-referred dead-zone size will limit accuracy • 90dB: dynamic pinch-off effects maintain high accuracy – weak inversion – saturation even for small V DS – gain-boosting from increased r o 1 0.65 Small Swing Small Swing 0.9 Medium Swing Medium Swing Large Swing Large Swing 0.8 0.7 Volts Volts 0.6 0.6 0.5 0.4 0.3 26 0.2 0.55 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 time (ns) time (ns)

Noise Suppression Max V OV 2 - 3 V DZ V OUT V IN 1 + • Output pinch-off reduces I D , g m – Internal noise sources attenuated • Initial charging noisy → final settling quiet 27

Noise Suppression Pinch-off 2 - 3 V DZ V OUT V IN 1 + • Output pinch-off reduces I D , g m – Internal noise sources attenuated • Initial charging noisy → final settling quiet 28

ADC Implementation Details

Structure Overview 1.5b: 1b + 0.5b redundancy (MDAC gain of 2 per stage) V IN + 1.5b 1.5b 1.5b 1.5b 1.5b 1.5b 1.5b 1.5b 1.5b 1.5b V IN - C U = 200 fF C U = 200 fF C U = 200 fF C U = 200 fF C U = 200 fF C U = 200 fF C U = 200 fF C U = 200 fF C U = 200 fF FLASH Uses Same Ringamp for all Stages FLASH • 10.5b Pipelined ADC – 9 identical 1.5b MDAC stages – 1.5b Flash • Simple proof-of-concept built to characterize: – Basic functionality – Rail-to-rail output swing – Noise immunity 30

Ring amplifier V RN 1X Φ S 2X 0.5X 1X 100fF Φ S V IN V OUT 1X 100fF 100fF 1X 0.5X 2X Φ S 1X V RP • Very small, very simple, uses minimum size inverters 31

Float-sampled MDAC Ф S Ф A Ф A 200fF V IN + Ф S V OUT + RAMP Ф A 200fF Ф SE D·V REF Ф SE V CMX -D·V REF Ф SE Ф A 200fF V OUT - RAMP Ф S V IN - Ф A 200fF Ф A Ф S • Differential gain: 2X • Common-mode gain: 1X 32

Measurement Results

Input Spectrum • Limited by quantization noise • Inherent noise advantage demonstrated 34

Rail-to-Rail Output Swing Test Rail-to-rail output swing test 60 V DD = 1.2V 55 V refp = 1.2V V refn = 0V 50 f s = 4MHz SNDR (dB) 45 40 35 30 25 20 -40 -35 -30 -25 -20 -15 -10 -5 0 Input Amplitude (dBFS) 35

Ring Amp Dead-Zone Sensitivity Ring Amplifier dead-zone sensitivity 65 60 SNDR (dB) 55 nominal value (40mV) 50 45 -20 0 20 40 60 80 100 1st stage dead-zone (mV differential pk-pk) 36

Performance Summary Technology 0.18µm 1P4M CMOS Resolution 10.5 bits Analog Supply 1.3 V Sampling rate 30 Msps ERBW 15 MHz Input Range 2.2 V pk-pk diff. SNDR 61.5 dB SNR 61.9 dB SFDR 74.2 dB ENOB 9.9 bits Total Power 2.6 mW FoM 90 fJ/c-step 37

Room for improvement • Design meant to probe THD, SNR limits of minimum sized ringamp – Speed set intentionally low – No optimization, stage scaling – Ringamps left ‘on’ during sampling phase – FoM can easily be improved • ISSCC 2012 implementation** – Speed: 90Msps – Power save features: 50% reduction in power ** B. Hershberg, et al. “Ring Amplifiers for Switched Capacitor Circuits”, ISSCC 2012 38

Scalability Test • Design Challenge: – MDAC for 11b pipelined ADC with 10b ENOB – 130nm, 90nm, 65nm, 45nm, 32nm V DD process defined SNDR > 66dB (input referred) Output Swing 0.8V DD Total Load 800fF Speed proportional to 1/L min Power Minimize – ASU predictive technology models [ptm.asu.edu] 39

Scalability Test V RN RST RST RST V RP Test Ringamp 40

Scalability Test Ф S Ф A Ф S 200fF V IN + RAMP 200fF Ф A Ф S 300fF Ф SE V CM V CMX Ф SE Ф S Ф A 300fF 200fF RAMP V IN - Ф S 200fF Ф A Ф S Pesudo-differential Test MDAC 41

Scalability Test P TOT / f s (P TOT - P CV 2 f ) / f s 0 10 Efficiency (pJ / cycle) 130nm 1.2V 100MHz 90nm 1.2V 150MHz 65nm -1 10 1.2V 32nm 200MHz 1.0V 420MHz 45nm -2 10 1.05V 300MHz 100 150 200 250 300 350 400 Conversion Speed (MHz) 42