1 Introduction Circuits for counting both forward and backward - PDF document

Long and Fast Up/Down Counters Pushpinder Kaur CHOUHAN 6 th Jan, 2003 1 Introduction Circuits for counting both forward and backward events are frequently used in computers and other digital systems. Digital clocks and watches are ev- erywhere, timers are found in a range of appliances from microwave ovens to VCRs and counters for other reasons are found in everything from auto- mobiles to test equipment. Since a counter circuit must remember its past states, it has to possess memory. For this purpose flip-flops are used. The number of flip-flops used and how they are connected determine the number of states and the sequence of the states that the counter goes through in each complete cycle. Although we will see many variations on the basic counter, they are all fundamentally very similar. The paper presents recent advances in the design of constant-time up/down counters in the general context of fast counter design. An overview of ex- isting techniques for the design of long and fast counters reveals several methods closely related to the design of fast adders, as well as some tech- niques that are only valid for counter design. The main idea behind the novel up/down counters is to recognize that the only extra difficulty with an up/down counter is when the counter changes direction from counting up to counting down (and vice-versa). For dealing with this difficulty, the new design uses a shadow register for storing the previous counter state. When counting only up or only down, the counter functions like a standard up-only or down-only constant time counter, but, when it changes direction instead of trying to compute the new value (which typically requires carry propa- gation), it simply uses the contents of the shadow register which contains the exact desired previous value. An alternative approach for restoring the previous state in constant time is to store the carry bits in a Carry/Borrow register . The simplest type of counter is the Binary Counter . The 2-bit ripple counter circuit has four different states, each one corresponding to a count value. Similarly, a counter with n flip-flops can have 2 n states. The number of states in a counter is known as its mod number . Thus a 2-bit counter is a mod-4 counter.A mod-n counter may also described as a divide-by-n counter because it can also be used to divide the input pulse frequency by factor of n(the mod number). Thus, the mod-4 counter is an example of a divide-by-4 counter. In general we can write counter as binary modulo-2 N N-bit counter where the value s(t) of the counter is incremented by one in each clock cycle: s(t+1)=s(t)mod2 N 1

Besides this basic behavior, most counter types have several other fea- tures, the most important ones being illustrated with the help of a “black- box” model as in Figure 1. Figure 1 . “Black-box” generic counter model with the most common control signals. 1. Resettable - The counter value is reset to all zeros when the RESET input is active. 2. Loadable - The counter is loaded with the N-bit value at the In input lines when the LOAD input is active. 3. Reversible - The counter counts “up” (increments) when the UP/DOWN input signal is inactive and counts“down”(decrements) when the UP/DOWN input signal is active. 4. Count-enable — The counter increments every clock cycle only when the CNT input is active. 5. Terminal Count — TC output signal active when the counter reaches the maximum value (all ones) counting up or reaches the minimum value (all zeros) when counting down. 6. Readable on-the-fly — The counter state (Out) can be read reliably with- out stopping the clock. Ideally, this sampling rate should be equal to the clock rate. 2 Counters 2.1 Asynchronous Counter A three-bit asynchronous counter is shown in Figure 2. The external clock is connected to the clock input of the first flip-flop (FF0) only. So, FF0 changes state at the falling edge of each clock pulse, but FF1 changes only when triggered by the falling edge of the Q output of FF0 and so on. Because of the inherent propagation delay through a flip-flop, the transition of the input clock pulse and a transition of the Q output of FF0 can never occur at exactly 2

the same time. Therefore, the flip-flops cannot be triggered simultaneously, producing an asynchronous operation. Figure 2 . Asynchronous counter. Usually, all the CLEAR inputs are connected together, so that a single pulse can clear all the flip-flops before counting starts. The clock pulse fed into FF0 is rippled through the other counters after propagation delays, like a ripple on water, hence the name Ripple Counter. 2.1.1 Asynchronous Up-Down Counters In certain applications a counter must be able to count both up and down. The circuit below is a 3-bit up-down counter. It counts up or down depend- ing on the status of the control signals UP and DOWN. When the UP input is at 1 and the DOWN input is at 0, the NAND network between FF0 and FF1 will gate the non-inverted output (Q) of FF0 into the clock input of FF1. Similarly, Q of FF1 will be gated through the other NAND network into the clock input of FF2. Thus the counter will count up. Figure 3 . Asynchronous Up-Down Counters. When the control input UP is at 0 and DOWN is at 1, the inverted outputs of FF0 and FF1 are gated into the clock inputs of FF1 and FF2 respectively. Notice that an asynchronous up-down counter is slower than an up counter or a down counter because of the additional propagation delay in- troduced by the NAND networks. 3

2.2 Synchronous Counter In synchronous counters, the clock inputs of all the flip-flops are connected together and are triggered by the input pulses. Thus, all the flip-flops change state simultaneously (in parallel). The circuit in Figure 4 is a 3-bit syn- chronous counter. The J and K inputs of FF0 are connected to HIGH. FF1 has its J and K inputs connected to the output of FF0, and the J and K inputs of FF2 are connected to the output of an AND gate that is fed by the outputs of FF0 and FF1. After the 3rd clock pulse, both outputs of FF0 and FF1 are HIGH. The positive edge of the 4th clock pulse will cause FF2 to change its state due to the AND gate. Figure 4 . Synchronous Counter. The most important advantage of synchronous counters is that there is no cumulative time delay because all flip-flops are triggered in parallel. Thus, the maximum operating frequency for this counter will be significantly higher than for the corresponding ripple counter. 2.2.1 Synchronous Up-Down Counters A circuit of a 3-bit synchronous up-down counter is shown in Figure 5. Sim- ilar to an asynchronous up-down counter, a synchronous up-down counter also has an up-down control input. It is used to control the direction of the counter through a certain sequence. Figure 5 . Synchronous Up-Down Counters. See the sequence shown in Table 1. For both the UP and DOWN sequences, Q0 toggles on each clock pulse. For the UP sequence, Q1 changes state on the next clock pulse when Q0=1. For the DOWN sequence, Q1 changes state on the next clock pulse when Q0=0. For the UP sequence, Q2 changes state on the next clock pulse when Q0=Q1=1. For the DOWN sequence, Q2 changes state on the next clock pulse when Q0=Q1=0. 4

Table 1 . Sequence Table. 2.3 Ring Counter The simplest shift register counter is a circulating shift register connected so that the last FF shifts its value into the first FF. The FFs are so connected so that information shifts from left to right and back around from Q0 to Q3. In most instances only a single 1 is in the register and it is made to circulate around the register as long as clock pulses are applied. Thus it is called a ring counter. Figure 6 . Ring Counter (a) Block Diagram; (b) Waveforms; (c) State Diagram; (d) Sequence Table. The waveforms, block diagram, sequence table and state diagram is shown in Figure 6. We have assumed the starting state of Q3=1 and Q2=Q1=Q0=0. This counter function as Mod-4 counter, since it has four distinct states before the sequence repeats. Although this circuit does not progress through the normal binary counting sequence, it is still a counter because each count correspond to unique set of FF states. Each FF output waveform has a frequency equal to one-fourth of the clock frequency. A Mod-N ring counter uses N flip-flops connected in the same arrangement as shown in Figure 6. 2.4 Twisted-tail Counter The basic ring counter can be modified slightly to produce another type of shift register counter, which will have somewhat different properties. The Twisted-ring counter is constructed exactly like a normal ring counter except 5