IREAP Nonlinear Effects in Advanced Communications Circuits Excited - PowerPoint PPT Presentation

IREAP Nonlinear Effects in Advanced Communications Circuits Excited by Pulsed RF John Rodgers, Todd M. Firestone and V. L. Granatstein Institute for Research in Electronics and Applied Physics University of Maryland College Park, MD 20742 jrodgers@glue.umd.edu

IREAP Program Goals • Investigate basic electronic mechanisms that cause RF-induced upset in communications circuits • Characterize device-level effects • Identify how susceptibility depends on: – RF power, frequency and modulation – Device type, voltage, size, layout, parasitic elements, etc. – Scaling laws: future devices will be smaller, faster, lower voltage • Develop basis for modeling RF effects

IREAP Outline • Overview of basic circuit elements excited by RF • Characterization of nonlinear and high frequency response • How upset depends on: – Input DC bias (Vbias) and supply (Vcc) voltages – RF characteristics (frequency, amplitude and modulation) – Logic family, ESD type and topology, – Chaotic excitation • High frequency circuit modeling using PSPICE • Nonlinear effects in wireless communications • Summary of accomplishments and future directions

IREAP Logic Families Tested at UMD Number in Service Source: “Logic Reference Guide,” Texas Instruments Inc., 2002.

IREAP Examples of Electrostatic Discharge (ESD) Protection Circuits in Advanced Logic Virtually all integrated circuits have some sort of ESD.

IREAP Consider What High Frequencies See RF Pulse ESD Vcc C(V,f) Diode L parasitic Bus Line Z Inverter Driver ESD C parasitic C(V,f) Diode Typical circuit values are resonant at microwave frequencies

IREAP Input Impedance at Microwave Frequencies: Dependence of Resonance on Input Bias 1000 0.5 0.4 Induced Amplitude [V] Impedance [Ohms] 100 0.3 Vbias= -0.70 Vbias= -0.60 0.2 Vbias= -0.50 10 Vbias= -0.40 Vbias= 0.0 0.1 Vbias= +2.0 Pulse Amplitude 1 0 0 0.5 1 1.5 2 Frequency [GHz]

IREAP LVX Family Input Impedance 100 Impedance [Ohms] Vbias= +0.0 Vbias= 0.5 Vbias= +1.0 Vbias= +1.5 Vbias= +2.5 10 0.5 1 1.5 2 Frequency [GHz]

IREAP Rectification of RF by Ground-Clamp ESD Diode 2 1.5 1 Voltage [V] 0.5 0 -0.5 0 50 100 150 200 Time [ns]

IREAP Direct Injection RF Test System VCC IN OUT CMOS Inverter Oscilloscope RF Amplifier DUT Load Spectrum RF Resistor Analyzer Bias-T Source Oscilloscope Pull-up Resistor Vbias

IREAP Voltage Induced at Input from Rectification of Microwave Pulse by ESD Diode (Frequency = 1.4 GHz, LVX Resonance) 3.5 3 RF-Induced Voltage at Input RF Amplitude 2.5 2 Voltage 1.5 1 0.5 0 0 25 50 75 100 Time [us]

IREAP Drive Characteristic of RF Rectification in ALVC (Frequency = 0.95 GHz, ALVC Resonance) 5 6 Rectified Voltage Rectified Voltage at Input [V] 4 Voltage Transfer [V/V] Vrect. / Vrf 4 3 2 2 1 0 0 0 0.2 0.4 0.6 0.8 RF Voltage at Input [V]

IREAP ALVC Response as RF Amplitude Increases 09_rodgers_alvc.avi

IREAP Logic Rise Time Matters : When Input Voltage is Near Switching Threshold, Device is Very Sensitive to RF 6 12 4 10 2 8 Voltage [V] V_out 0 6 V_bias RF -2 4 -4 2 -6 0 0 50 100 150 200 Time [us]

IREAP Input State Matters : Comparison of ALVC Output Voltage with High and Low Input Levels and RF Excitation 5 4 Outout Voltage 3 2 1 0 -1 0 100 200 300 400 Time (ns) Vih Vil

IREAP Input IV Characteristics of ALVC (has both Vcc and ground clamp diodes) V hi V lo

IREAP ESD Device-Type Matters : Comparison of HCT Susceptibility with High and Low Input Levels (HCT grounded gate NMOS clamp) 5 which causes output state change 0 Threshold RF Power [dBm] -5 -10 -15 -20 -25 -30 1 2 3 4 5 Frequency (GHz) Bias=0.4V Bias=2.4V

IREAP ESD Topology Matters : Comparison of rectified pulse amplitudes in devices w/ ESD ground clamp, V cc clamp, and both (input biased low state) 5 VHC_gnd only Rectified Pulse Amplitude [V] LVC_gnd + Vcc zener 4 HCT_ggNMOS 3 LVX_Vcc only 2 1 0 0.5 0.75 1 1.25 1.5 1.75 2 Frequency [GHz]

IREAP CMOS Characteristics Matter : Comparison of devices with wide and narrow input voltage bands where both MOS transistors are conducting Vin

IREAP When RF biases both CMOS transistors into conduction, device becomes unstable and noisy. Other nonlinear effects have also been observed (possibly chaotic oscillations). Tail End of LVX Input and Output Voltages as RF Pulse Terminates 2.5 2 Vin 1.5 Voltage 1 Vout 0.5 0 4 5 6 7 8 Time [microseconds]

IREAP Operating Voltages Matter: Typically, devices are more susceptible to RF as Vcc decreases and the switching (threshold) voltage band narrows. -15 Vcc=5 Threshold RF Power [dBm] -20 Vcc=4 to cause state change Vcc=3 -25 -30 -35 -40 0 0.5 1 1.5 Vbias (V)

IREAP Modulation Matters : Comparison of CW and Pulsed Excitations at Same Power Level LVX Upset Threshold 40 35 Injected Power [dBm] 30 25 20 15 10 5 0 1 1.2 1.4 1.6 1.8 2 2.2 Frequency [GHz] Pulsed RF CW

IREAP Injection of RF Pulse with Chaotic Amplitude Attenuator Vbias Vout 30 dB 20 dB Bias Tee Hughes 8537H DUT= ALVC TWTA 20 dB Spectrum Variable Atten. Analyzer RF Detector Delay Line Scope

IREAP Amplitude of TWT Output 0.18 0.16 0.14 0.12 Amplitude [det] 0.1 0.08 0.06 0.04 0.02 0 0 0.5 1 1.5 2 2.5 3 3.5 4 Time [us]

IREAP Attractor Map of TWTA Amplitude 0 -0.05 -0.1 A(t-7tau/4) -0.15 -0.2 -0.25 -0.3 -0.35 -0.35 -0.3 -0.25 -0.2 -0.15 -0.1 -0.05 0 A(t)

IREAP Spectrum of RF Pulse from TWT -15 -25 Spectral Power [dBm] -35 -45 -55 -65 -75 0 1 2 3 4 5 6 7 Frequency [GHz]

IREAP Output of ALVC Device w/ “Chaotic” Input 6 5 4 3 Voltage [V] 2 1 0 -1 -2 -3 0 1 2 3 4 5 6 Time [microseconds]

IREAP High Frequency Spice Modeling

IREAP Spice model includes: • Package and bonding parasitics • High frequency characteristics of Vcc bypass capacitor: inductance, ESR • ESD diodes: reverse recovery, C j (V), R f , etc. • External parasitics on ground and Vcc buses.

IREAP Spice simulation of ALVC output voltage with input excited by RF pulse

IREAP Studies of RF Effects in Wireless Communications and Mixed Signal Systems (e.g. Bluetooth) Synthesized LO RF Amp/ Mixer RF Pulse Input Demodulator Power Supply Baseband Output

IREAP Schematic of a “loop-back” test circuit for investigating RF effects in digital communications systems and components Probe Probe Probe Probe Probe Probe Mixer ADC Probe LNA SAW Filter BP Filter In LO RAM Logic Out Mixer DAC LNA SAW Filter BP Filter LO Find possible RF entry points, pathways and circuit effects that may upset the system or corrupt data.

IREAP RF Effects on Baseband “Bluetooth” Signal 3 rd Harmonic Intermods 20 0.5 Signal 0.5 Baseband Signal [V] 15 Baseband [V] RF Detector 0 0.25 10 0 -0.5 -0.25 5 -0.5 0 -1 0 100 200 300 400 0 100 200 300 400 Time [arb] Time [arb] No RF Pulse With RF Pulses

IREAP The Effect of Noise on Digital RF Signals Digital communications signal plus noise or interference: − ω + φ +Φ = + + j ( t [ ] t ( )) t V t ( ) ( V V [ ] t V ( )) t e N 0 M N Noisy QAM 64 Constellation

IREAP Results of 3rd Harmonic Injection (1.129 GHz at IF Stage) 0.1 RMS Baseband Amplitude [V] 0.08 0.06 Noise Margin for QAM 256 0.04 0.02 0 -60 -55 -50 -45 -40 -35 -30 -25 -20 Injection Power [dBm] Plot of RMS amplitude of the baseband interference signal vs. RF pulse power.

IREAP Summary of Results • RF pulses are detected by nonlinear circuit elements. • Susceptibility depends on ESD type and topology, parasitic resonances, bias and supply voltages. • Demodulated RF pulses mimics valid logic states and cause state change. • Faster, smaller, lower voltage devices are more susceptible at low power levels and higher frequencies. • Susceptibility enhanced by parasitic resonant frequencies, which increase as operating speed increases. • Other nonlinear effects (bias shift, oscillation, noise) disrupt data even if output state does not latch.

IREAP Collaborations • Jaycor/Titan interested in results for model development – Visit resulted in agreement to share experimental data. – First installment CD sent 10/03 containing test result for most advanced CMOS families. – Second installment will be sent by 12/03 containing general high frequency device characteristics. • MRC has expressed interest in possible collaboration. • Philips Semiconductor: – UMD requested information on Phillips ESD circuits. – The Phillips Engineering Applications chief contacted UMD to arrange a phone meeting to discuss possible collaboration. He expressed extreme interest in the project. – Phillips and UMD will be executing a nondisclosure agreement whereby they will share proprietary design data on ESD. – They recently sent us proprietary SPICE models and an internal handbook on modeling high frequency package parasitics.