VLSI Testing Yield and Fault Modeling Virendra Singh Associate Professor Computer Architecture and Dependable Systems Lab Department of Electrical Engineering Indian Institute of Technology Bombay http://www.ee.iitb.ac.in/~viren/ E-mail: viren@ee.iitb.ac.in Testing & Verification of VLSI Circuits Lecture 5 CADSL
Costs of Testing • Design for testability (DFT) – Chip area overhead and yield reduction – Performance overhead • Software processes of test – Test generation and fault simulation – Test programming and debugging • Manufacturing test – Automatic test equipment (ATE) capital cost – Test center operational cost 24 Jan 2013 EE-709@IITB 2 CADSL
Design for Testability (DFT) DFT refers to hardware design styles or added hardware that reduces test generation complexity. Motivation: Test generation complexity increases exponentially with the size of the circuit. Example: Test hardware applies tests to blocks A and B and to internal bus; avoids test generation for combined A and B blocks. Int. Primary Primary Logic bus Logic outputs inputs block A block B (PO) (PI) Test Test input output 24 Jan 2013 EE-709@IITB 3 CADSL
Testing Principle 24 Jan 2013 EE-709@IITB 4 CADSL
ADVANTEST Model T6682 ATE 24 Jan 2013 EE-709@IITB 5 CADSL
Cost of Manufacturing Testing • 0.5-1.0GHz; analog instruments; 1,024 digital pins: ATE purchase price = $1.2M + 1,024 x $3,000 = $4.272M • Running cost (five-year linear depreciation) = Depreciation + Maintenance + Operation = $0.854M + $0.085M + $0.5M = $1.439M/year • Test cost (24 hour ATE operation) = $1.439M/(365 x 24 x 3,600) = 4.5 cents/second 24 Jan 2013 EE-709@IITB 6 CADSL
Cost Analysis Graph 100 40,000 l a t o T Fixed, Total and Variable t s o Average Cost (cents) c Fixed cost 25,000 Costs ($) 20,000 50 Average cost Variable cost 0 0 0 50k 100k 150k 200k Miles Driven 24 Jan 2013 EE-709@IITB 7 CADSL
A Modern VLSI Device System-on-a-chip (SOC) DSP RAM core ROM Transmission Data medium terminal Inter- Mixed- face signal logic Codec 24 Jan 2013 EE-709@IITB 8 CADSL
VLSI Chip Yield A manufacturing defect is a finite chip area with electrically malfunctioning circuitry caused by errors in the fabrication process. A chip with no manufacturing defect is called a good chip. Fraction (or percentage) of good chips produced in a manufacturing process is called the yield . Yield is denoted by symbol Y . Cost of a chip : Cost of fabricating and testing a wafer -------------------------------------------------------------------- Yield x Number of chip sites on the wafer 24 Jan 2013 EE-709@IITB 9 CADSL
Clustered VLSI Defects Good chips Faulty chips Defects Wafer Clustered defects (VLSI) Unclustered defects Wafer yield = 17/22 = 0.77 Wafer yield = 12/22 = 0.55 24 Jan 2013 EE-709@IITB 10 CADSL
Yield Parameters Defect density ( d ) = Average number of defects per unit of chip area Chip area ( A ) Clustering parameter (α) Negative binomial distribution of defects, p ( x ) = Prob (number of defects on a chip = x ) Γ ( α + x ) ( Ad / α ) x = ------------- . ---------------------- x ! Γ ( α ) (1+ Ad / α ) α + x where Γ is the gamma function α = 0, p ( x ) is a delta function (maximum clustering) α = ∞ , p ( x ) is Poisson distribution (no clustering) 24 Jan 2013 EE-709@IITB 11 CADSL
Yield Equation Y = Prob ( zero defect on a chip ) = p (0) Y = ( 1 + Ad / α ) − α Example: Ad = 1.0, α = 0.5, Y = 0.58 Unclustered defects: α = ∞, Y = e - Ad Example: Ad = 1.0, α = ∞, Y = 0.37 too pessimistic ! 24 Jan 2013 EE-709@IITB 12 CADSL
Defect Level or Reject Ratio Defect level (DL) is the ratio of faulty chips among the chips that pass tests. DL is measured as parts per million (ppm). DL is a measure of the effectiveness of tests. DL is a quantitative measure of the manufactured product quality. For commercial VLSI chips a DL greater than 500 ppm is considered unacceptable. 24 Jan 2013 EE-709@IITB 13 CADSL
Determination of DL From field return data: Chips failing in the field are returned to the manufacturer. The number of returned chips normalized to one million chips shipped is the DL. From test data: Fault coverage of tests and chip fallout rate are analyzed. A modified yield model is fitted to the fallout data to estimate the DL. 24 Jan 2013 EE-709@IITB 14 CADSL
Modified Yield Equation • Three parameters: Fault density, f = average number of stuck-at faults per unit chip area Fault clustering parameter, β Stuck-at fault coverage, T • The modified yield equation: Y ( T ) = (1 + TAf / β ) - β Assuming that tests with 100% fault coverage ( T =1.0) remove all faulty chips, Y = Y (1) = (1 + Af / β ) - β 24 Jan 2013 EE-709@IITB 15 CADSL
Defect Level Y ( T ) - Y (1) DL ( T ) = -------------------- Y ( T ) ( β + TAf ) β = 1 - -------------------- ( β + Af ) β Where T is the fault coverage of tests, Af is the average number of faults on the chip of area A , β is the fault clustering parameter. Af and β are determined by test data analysis. 24 Jan 2013 EE-709@IITB 16 CADSL
Yield and Fault Coverage 3 0 2 5 D e f e c t L e v e l 2 0 1 5 1 0 5 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 F a u l t C o v e r a g e 24 Jan 2013 EE-709@IITB 17 CADSL
Computed DL 237,700 ppm ( Y = 76.23%) Defect level in ppm Stuck-at fault coverage (%) SEMATECH Chip (Courtesy: IBM) 24 Jan 2013 EE-709@IITB 18 CADSL
Time to Market L o s s o f R e v e n u e s R e v e n u e s T i m e t o T i m e i n M o n t h s M a r k e t ∆ T 24 Jan 2013 EE-709@IITB 19 CADSL
Failure Rate Vs Product Lifetime 24 Jan 2013 EE-709@IITB 20 CADSL
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