Overview Motivation About the Course and the Instructor ECE 553: - PDF document

8/14/2014 Overview • Motivation • About the Course and the Instructor ECE 553: TESTING AND – Conduct TESTABLE DESIGN OF – Outline – Coursepack DIGITAL SYSTES DIGITAL SYSTES • Introduction – VLSI realization process – Contract between design house and fab vendor – Test v/s verification – Need for testing: doing business, ideal v/s real testing – Levels of testing – rule of 10 (or 20) Motivation and Introduction – Cost of manufacturing 8/14/2014 2 Motivation: Moore’s Law Complexity Growth of VLSI circuits Motivation Source (Copp, Int. AOC EW Conf., 2002 ) • Where do the manufacturing $ go? • Overhead of one or two photomicrographs – What is test on a chip? • Course conduct – Your responsibilities and mine • Course outline • Course material information – References and reading material 8/14/2014 3 8/14/2014 4 Moore’s Law – Other Effects 8/14/2014 5 8/14/2014 6 1

8/14/2014 Thermal Effect of Moore’s law Introduction: Challenges under deep submicron technologies (Yao) Source: Intel Source: Intel  Moore’s law Greater packaging densities Higher power densities Chip size decreases Power density increases Power density increases Higher temperature  Effects  Reliability  Performance  Power  Cooling cost Source: Wang et al. ISPD2003 Chip becomes hotter Leakage power make it worse 8/14/2014 7 Microprocessor Cost per Transistor VLSI Realization Process Cost of testing will EXCEED cost of design/manufacturing ( Source: ITR-Semiconductor, 2002) Customer’s need Determine requirements Write specifications Design synthesis and Verification D i th i d V ifi ti Test development Fabrication Manufacturing test Chips to customer 8/14/2014 9 8/14/2014 10 Contract between a design house Present and Future and a fab vendor • Design is complete and checked (verified) Technology Directions: SIA Roadmap • Fab vendor: How will you test it? Year 1999 2002 2005 2008 2011 2014 • Design house: I have checked it and … Feature size (nm) 180 130 90 45 32 22 • Fab vendor: But, how would you test it? Mtrans/cm 2 7 14-26 47 115 284 701 Chi Chip size (mm 2 ) i ( 2 ) 170 170 170-214 170 214 235 235 269 269 308 308 354 354 • Desing house: Why is that important? It is between Signal pins/chip 768 1024 1024 1280 1408 1472 I and my clients – it is none of your business Clock rate (MHz) 600 800 1100 1400 1800 2200 • Fab vendor – Sorry you can take your business Wiring levels 6-7 7-8 8-9 9 9-10 10 some where else. Power supply (V) 1.8 1.5 1.2 0.9 0.6 0.6 High-perf power (W) 90 130 160 170 174 183 complete the story and determine the reasons for the Battery power (W) 1.4 2.0 2.4 2.0 2.2 2.4 importance of test generation etc. http://www.itrs.net/ntrs/publntrs.nsf 8/14/2014 12 2

8/14/2014 Verification v/s Testing Contract between design … Hence: Definitions • “Test” must be comprehensive • Design synthesis: Given an I/O function, develop a procedure to manufacture a device using known • It must not be “too long” materials and processes. Issues: Issues: • Verification: Predictive analysis to ensure that the • Model possible defects in the process synthesized design, when manufactured, will perform the – Understand the process given I/O function. • Develop logic simulator and fault simulator • Test: A manufacturing step that ensures that the physical • Develop test generator device, manufactured from the synthesized design, has • Methods to quantify the test efficiency no manufacturing defect. 8/14/2014 13 8/14/2014 14 Need for testing Verification v/s Testing • Verifies correctness of • Verifies correctness of • Functionality issue design. manufactured hardware. – Does the circuit (large or small) work? • Performed by simulation, • Two-part process: • Density issue hardware emulation, or – 1. Test generation: software process – Higher density  higher failure probability executed once during design executed once during design formal methods. formal methods • Application issue – 2. Test application: electrical tests • Performed once prior to applied to hardware – Life critical applications manufacturing. • Test application performed on • Maintenance issue • Responsible for quality of every manufactured device. – Need to identify failed components design. • Responsible for quality of devices. • Cost of doing business • What does testing achieve? – Discard only the “bad product”? – see next three slides 8/14/2014 15 8/14/2014 16 Problems of Ideal Tests Real Tests • Based on analyzable fault models, which may not • Ideal tests detect all defects produced in the map on real defects. manufacturing process. • Incomplete coverage of modeled faults due to high • Ideal tests pass all functionally good devices • Ideal tests pass all functionally good devices. complexity. complexity • Some good chips are rejected. The fraction (or • Very large numbers and varieties of possible percentage) of such chips is called the yield loss. defects need to be tested. • Some bad chips pass tests. The fraction (or • Difficult to generate tests for some real defects. percentage) of bad chips among all passing chips Defect-oriented testing is an open problem. is called the defect level. 8/14/2014 17 8/14/2014 18 3

8/14/2014 Testing as Filter Process Levels of testing (1) • Levels Mostly Good chips Prob(pass test) = high good – Chip Prob(good) = y chips – Board – System y Fabricated • Boards put together chips • System-on-Chip (SoC) – System in field Mostly Defective chips • Cost – Rule of 10 bad Prob(bad) = 1- y – It costs 10 times more to test a device as we move to Prob(fail test) = high chips higher level in the product manufacturing process 8/14/2014 19 8/14/2014 20 Levels of testing (2) Cost of Testing • Design for testability (DFT) • Other ways to define levels – these are important to develop correct “fault models” and “simulation – Chip area overhead and yield reduction models” – Performance overhead – Transistor • Software processes of test – Gate G t – Test generation and fault simulation – RTL – Test programming and debugging – Functional • Manufacturing test – Behavioral – Automatic test equipment (ATE) capital cost – Architecture – Test center operational cost • Focus: Chip level testing – gate level design 8/14/2014 21 8/14/2014 22 Cost of Manufacturing Testing in Roles of Testing 2010+ • Detection: Determination whether or not the device • 0.5-1.0GHz, analog instruments,1024 digital pins: under test (DUT) has some fault. ATE purchase price • Diagnosis: Identification of a specific fault that is – = $4.0M + 1,024 x $5,000 = $9.12M present on DUT. • Running cost (five-year linear depreciation) Running cost (five year linear depreciation) • Device characterization: Determination and – = Depreciation + Maintenance + Operation correction of errors in design and/or test procedure. – = $1.80M + $0.185M + $1.5M • Failure mode analysis (FMA): Determination of – = $3.485M/year manufacturing process errors that may have caused • Test cost (24 hour ATE operation) defects on the DUT. – = $3.485M/(365 x 24 x 3,600) – = 11.05 cents/second 8/14/2014 23 8/14/2014 24 4

8/14/2014 Summary • About the course • Expectations • Why test? • Cost issue – First look 8/14/2014 25 5