VLSI Testing Sequential ATPG Virendra Singh Associate Professor C omputer A rchitecture and D ependable S ystems L ab Department of Electrical Engineering Indian Institute of Technology Bombay http://www.ee.iitb.ac.in/~viren/ E-mail: viren@ee.iitb.ac.in EE-709: Testing & Verification of VLSI Circuits Lecture 17 (28 Feb 2013) CADSL
Sequential Circuits A sequential circuit has memory in addition to combinational logic Test for a fault in a sequential circuit is a sequence of vectors, which Initializes the circuit to a known state Activates the fault, and Propagates the fault effect to a PO Methods of sequential circuit ATPG Time-frame expansion methods Simulation-based methods 28 Feb 2013 EE-709@IITB 2 CADSL
Example: A Serial Adder B n A n 1 1 s-a-0 D 1 1 D X C n C n+1 X 1 Combinational logic X S n FF 28 Feb 2013 EE-709@IITB 3 CADSL
Time-Frame Expansion B n-1 A n-1 A n B n Time-frame -1 Time-frame 0 1 1 1 1 s-a-0 s-a-0 D X D D 1 1 D 1 C n-1 X D C n 1 1 C n+1 X 1 Combinational logic Combinational logic 1 S n-1 S n X D FF 28 Feb 2013 EE-709@IITB 4 CADSL
Concept of Time-Frames If the test sequence for a single stuck-at fault contains n vectors , Replicate combinational logic block n times Place fault in each block Generate a test for the multiple stuck-at fault using combinational ATPG with 9-valued logic Vector - n +1 Vector -1 Vector 0 Fault Unknown Next State Time- Time- Time- or given state variables frame frame frame Init. state 0 - n +1 -1 Comb. block PO - n +1 PO -1 PO 0 28 Feb 2013 EE-709@IITB 5 CADSL
Example for Logic Systems FF1 B A FF2 s-a-1 28 Feb 2013 EE-709@IITB 6 CADSL
Five-Valued Logic (Roth) A 0 A 0 s-a-1 s-a-1 D D X X X FF1 FF1 X D D FF2 FF2 B B X X Time-frame 0 Time-frame -1 28 Feb 2013 EE-709@IITB 7 CADSL
Nine-Valued Logic (Muth) A 0 A X s-a-1 s-a-1 X /1 0/1 0/ X 0/ X X FF1 FF1 0/1 X X /1 FF2 FF2 B B X 0/1 Time-frame Time-frame -0 28 Feb 2013 EE-709@IITB 8 CADSL
Implementation of ATPG Select a PO for fault detection based on drivability analysis. Place a logic value, 1/0 or 0/1, depending on fault type and number of inversions. Justify the output value from PIs, considering all necessary paths and adding backward time-frames. If justification is impossible, select another PO and repeat justification (use drivability). If the procedure fails for all reachable POs, then the fault is untestable. If 1/0 or 0/1 cannot be justified at any PO, but 1/X or 0/X can be justified, the the fault is potentially detectable. 28 Feb 2013 EE-709@IITB 9 CADSL
Complexity of ATPG Synchronous circuit -- All flip-flops controlled by clocks; PI and PO synchronized with clock: Cycle-free circuit – No feedback among flip-flops: Test generation for a fault needs no more than dseq + 1 time-frames, where dseq is the sequential depth. Cyclic circuit – Contains feedback among flip- flops: May need 9 Nff time-frames, where Nff is the number of flip-flops. Asynchronous circuit – Higher complexity! Smax Time- Time- Time- Time- Time- S2 S3 S1 S0 Frame Frame Frame Frame Frame max-1 max-2 -2 -1 0 max = Number of distinct vectors with 9-valued elements = 9 Nff 28 Feb 2013 EE-709@IITB 10 CADSL
Cycle-Free Circuits Characterized by absence of cycles among flip-flops and a sequential depth, dseq . dseq is the maximum number of flip- flops on any path between PI and PO. Both good and faulty circuits are initializable. Test sequence length for a fault is bounded by dseq + 1. 28 Feb 2013 EE-709@IITB 11 CADSL
Cycle-Free Example Circuit F2 2 F3 F1 3 Level = 1 F2 2 s - graph F3 F1 dseq = 3 3 Level = 1 All faults are testable. 28 Feb 2013 EE-709@IITB 12 CADSL
Cycle-Free Example 0 1 2 -1 28 Feb 2013 EE-709@IITB 13 CADSL
Difficulties in Seq. ATPG Poor initializability. Poor controllability/observability of state variables. Gate count, number of flip-flops, and sequential depth do not explain the problem. Cycles are mainly responsible for complexity. An ATPG experiment: Circuit Number of Number of Sequential ATPG Fault gates flip-flops depth CPU s coverage TLC 355 21 14* 1,247 89.01% Chip A 1,112 39 14 269 98.80% * Maximum number of flip-flops on a PI to PO path 28 Feb 2013 EE-709@IITB 14 CADSL
Benchmark Circuits Circuit s1196 s1238 s1488 s1494 PI 14 14 8 8 PO 14 19 14 19 FF 6 18 18 6 Gates 529 508 653 647 Structure Cycle-free Cycle-free Cyclic Cyclic Sequential depth 4 4 -- -- Total faults 1242 1355 1486 1506 Detected faults 1283 1379 1239 1384 Potentially detected faults 2 0 0 2 Untestable faults 3 72 26 30 Abandoned faults 0 0 76 97 Fault coverage (%) 99.8 94.7 93.1 91.6 Fault efficiency (%) 100.0 100.0 94.8 93.4 Max. sequence length 3 3 28 24 Total test vectors 308 559 313 525 Gentest CPU s (Sparc 2) 10 15 19941 19183 28 Feb 2013 EE-709@IITB 15 CADSL
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