vhdl syntheses subset
play

VHDL Syntheses Subset 1 Combinational Logic Simple Signal - PowerPoint PPT Presentation

Nov 18, 2022 •191 likes •412 views

VHDL Syntheses Subset 1 Combinational Logic Simple Signal Assignment Conditional Signal Assignment Selected Signal Assignment Relational and Arithmetic Operators(excp DIV/MODE/**) Three State LOOP,CASE,IF 2 General

  1. VHDL Syntheses Subset 1

  2. Combinational Logic • Simple Signal Assignment • Conditional Signal Assignment • Selected Signal Assignment • Relational and Arithmetic Operators(excp DIV/MODE/**) • Three State • LOOP,CASE,IF 2

  3. General Style Process(rhs signals) variable declarations Begin a<=“000”; if(v=‘1’) then z:=a; y<=b; elsif a<=“0101”; end if; End process; 3

  4. Sequential Logic • Using edge detection and IF statement within Process 4

  5. Asynchronous Set/Reset Process(clk,set,reset) Begin if(set=‘1’) then stmt1; elsif(reset=‘1’) then stmt2; elsif(clk’event and clk=‘1’) then stmt3; end if; End process; 5

  6. Synchronous Set/Reset Process(clk,set,reset) Begin If(clk’event and clk=‘1’) then if(set=‘1’) then stmt1; elsif(reset=‘1’) then stmt2; else stmt3; end if; End if; End process; 6

  7. Synchronous with enable Process(clk,set,reset) Begin If(clk’event and clk=‘1’) then if(Enable=‘1’) then stmt1; end if; End if; End process; 7

  8. Counters Process(clk,set,reset) Begin If(clk’event and clk=‘1’) then Counter<=Counter+1; End if; End process; 8

  9. State Machines Process(clk) Begin If(reset=‘1’) CurrentState<=st1; elsIf(clk’event and clk=‘1’) then Case CurrentState IS when st1=> if(input=val1) next_state;=st3; end if; when st2=> if(input=val2) next_state:=st1; end if when st3=> if(input=val1) next_state:=st2; end if when others=> next_state:=st1; End case; End if; CurentState<=next_state; If(CurrentState=st2) then z<=‘1’ end if; End process; 9

  10. Chapter 10 Parwan Dataflow Model 10

  11. Dataflow Model DBUS Memory Memory DATABUS AR OFFSET AR PAGE AC PC PAGE PC OFFSET IR Alu Alu DBUS Controller Controller SHU SHU MAR BUS StR AR_PAGE AR_OFFSET ADBUS OBUS 11

  12. In/Out of Parwan Controller Applies To Category Signal Name AC REG load_ac,zero_ac IR REG load_ir MAR REG load_page_mar,load_offset_mar SR REG load_sr,cm_carry_sr PC REG increment_pc,load_page_pc,load_offset_pc,reset_pc MAR_BUS BUS pc_on_mar_page_bus, ir_on_mar_page_bus, pc_on_mar_offset_bus, ir_on_mar_offset_bus DBUS BUS pc_offset_on_dbus,obus_on_dbus,databus_on_dbus ADBUS BUS mar_on_adbus DATABUS BUS dbus_on_databus SHU LOGIC arith_shift_left, Arith_shift_right, ALU LOGIC alu_and,alu_not,alu_a,alu_add,alu_b,alu_sub OTHERS I/O read_mem,write_mem,interrupt 12

  13. ALU description ENTITY alu IS PORT (a_side,b_side:IN byte; alu_and,alu_not,alu_a,alu_add,alu_b,alu_sub : IN qit; flags_in : IN nibble; flag_out: OUT nibble; z: OUT byte ); 13

  14. ALU description ARCHITECTURE behavioral OF alu IS BEGIN Coding:PROCESS( alu_and,alu_not,alu_a,alu_add,alu_b,a lu_sub,flag_in,a_side,b_side) VARIABLE t:qit_vector( 9 downto 0); VARIABLE v,c,n,z:qit; ALIAS n_flag_in: qit IS in_flag(0); ALIAS z_flag_in: qit IS in_flag(1); ALIAS c_flag_in: qit IS in_flag(2); ALIAS v_flag_in: qit IS in_flag(3); 14

  15. ALU description BEGIN CASE qit_vector(5 downto 0)’(alu_and,alu_not,alu_a,alu_add,alu_b,alu_sub) IS WHEN a_add_b => t:=add_cv(b_side,a_side,c_flag_in); c:=t(8); v:=t(9); WHEN a_sub_b => t:=sub_cv(b_side,a_side,c_flag_in); c:=t(8); v:=t(9); WHEN a_and_b => t(7 downto 0):=b_side AND a_side; c:=c_flag_in; v:=v_flag_in; WHEN a_input => t(7 downto 0):=a_side; c:=c_flag_in; v:=v_flag_in; 15

  16. ALU description WHEN b_input => t(7 downto 0):=b_side; c:=c_flag_in; v:=v_flag_in; WHEN b_compl => t(7 downto 0):=NOT b_side; c:=c_flag_in; v:=v_flag_in; WHEN OTHERS => NULL: END CASE; n:=t(7); Z:=set_if_zero(t(7 downto 0)); Out_flag<=(v,c,z,n); END PROCESS codeing; END behavioral; 16

  17. Shifter Unit ENTITY Sifter_unit IS PORT( alu_side: IN byte; arith_shift_left,arith_shift_right: in qit; flag_in: nibble; flag_out:nibble; obus_side: byte ); 17

  18. Shifter Unit ARCHITECTURE behavioral of shifter_unit is BEGIN Codeing:PROCESS(alu_side,arith_shift_left ,arith_shift_right) VARIABLE t:qit_vector( 7 downto 0); VARIABLE v,c,n,z:qit; ALIAS n_flag_in: qit IS in_flag(0); ALIAS z_flag_in: qit IS in_flag(1); ALIAS c_flag_in: qit IS in_flag(2); ALIAS v_flag_in: qit IS in_flag(3); 18

  19. Shifter Unit BEGIN IF( arith_shift_left=‘0’ AND arith_shift_right=‘0’) then t:=alu_side(7 downto 0); (v,c,z,n):=flag_in; ELSIF(arith_shift_left=‘1’ ) then t:=alu_side(6 downto 0) & ‘0’; n:=t(7); z:=set_if_zero(t); c:=alu_side(7); v:=alu_side(6) XOR alu_side(7); 19

  20. Shifter Unit ELSIF(arith_shift_right=‘1’ ) then t:= alu_side(7) & alu_side(6 downto 0); n:=t(7); z:=set_if_zero(t); c:=c_flag_in; v:=v_flag_in; END IF; obus<=t; flag_out<=(v,c,z,n); END PROCESS; END; 20

  21. Status Register ENTITY sr IS PORT( in_flags: IN nibble; out_flags: OUT nibble; load,cm_carry,ck: IN qit ); END; 21

  22. Status Register ARCHITECTURE behavioral OF sr IS BEGIN PROCESS(ck) variable internal_state:nibble:=“0000”; alias internal_c:qit is internal_state(2); BEGIN if( ck=‘0’) then if(load=‘1’) then internal_state:=in_flags; end if; elsif(cm_carry=‘1’) then internal_c:=NOT internal_c; end if; out_status<=internal_state; END PROCESS; END; 22

Recommend

Introduction One of the possibilities to sophisticate compound syntheses is catalysis using

Introduction One of the possibilities to sophisticate compound syntheses is catalysis using

ONE-POT SYNTHESES USING CARBONYL COMPOUNDS CATALYZED BY CE(III) SUPPORTED ON A WEAKLY ACIDIC CATION-EXCHANGER RESIN Eva Havrnkov , Pavel Pazdera* *E-mail: pazdera@chemi.muni.cz, havrankovae@gmail.com Centre for Syntheses at Sustainable

576 views • 12 slides
Hardware Design with VHDL VHDL Essentials I ECE 443 Fundamental Elements of VHDL A VHDL program

Hardware Design with VHDL VHDL Essentials I ECE 443 Fundamental Elements of VHDL A VHDL program

Hardware Design with VHDL VHDL Essentials I ECE 443 Fundamental Elements of VHDL A VHDL program consists of a collection of design units , each of which is defined using three components Library and Package Declaration library IEEE; use

199 views • 15 slides
Hardware Design with VHDL Synthesis of VHDL Code ECE 443 Synthesis of VHDL Code This slide set

Hardware Design with VHDL Synthesis of VHDL Code ECE 443 Synthesis of VHDL Code This slide set

Hardware Design with VHDL Synthesis of VHDL Code ECE 443 Synthesis of VHDL Code This slide set covers Fundamental limitation of EDA software Realization of VHDL operator Realization of VHDL data type VHDL synthesis flow

511 views • 34 slides
Hardware Design with VHDL VHDL Basics ECE 443 Skeleton of a Basic VHDL Program This slide set

Hardware Design with VHDL VHDL Basics ECE 443 Skeleton of a Basic VHDL Program This slide set

Hardware Design with VHDL VHDL Basics ECE 443 Skeleton of a Basic VHDL Program This slide set covers the components to a basic VHDL program, including lexical ele- ments, program format, data types and operators A VHDL program consists of a

502 views • 34 slides
Hardware Design with VHDL VHDL I ECE 443 VHDL Introduction A language for describing the

Hardware Design with VHDL VHDL I ECE 443 VHDL Introduction A language for describing the

Hardware Design with VHDL VHDL I ECE 443 VHDL Introduction A language for describing the structural, physical and behavioral characteristics of digital systems. VHDL is used to attain several goals: Synthesis of digital systems.

539 views • 11 slides
VHDL VHDL - Flaxer Eli Ch 1 - 1 Inroduction Course Objectives Affected Write functionally

VHDL VHDL - Flaxer Eli Ch 1 - 1 Inroduction Course Objectives Affected Write functionally

Chapter 1 Introduction to VHDL VHDL VHDL - Flaxer Eli Ch 1 - 1 Inroduction Course Objectives Affected Write functionally correct and well-documented VHDL code , intended for either simulation or synthesis, of any combinational or

245 views • 7 slides
VHDL VHDL - Flaxer Eli Ch 8 - 1 VHDL - Flaxer Eli Ch 8 - 2 Structural Modeling Structural

VHDL VHDL - Flaxer Eli Ch 8 - 1 VHDL - Flaxer Eli Ch 8 - 2 Structural Modeling Structural

Chapter 8 Outline Structural Modeling Basic Example Component Declaration Component Instantiation Resolving Signal Value Generate Statement VHDL VHDL - Flaxer Eli Ch 8 - 1 VHDL - Flaxer Eli Ch 8 - 2 Structural Modeling

266 views • 5 slides
VHDL Description Models VHDL VHDL can be looked at as a model of a digital system

VHDL Description Models VHDL VHDL can be looked at as a model of a digital system

VHDL Description Models VHDL VHDL can be looked at as a model of a digital system Powerful alternative to schematic based design A change (transition) on the input may lead to a new system state and consequently a change of the

763 views • 15 slides
Hardware Design with VHDL Course Introduction ECE 443 Hardware Design with VHDL Instructors:

Hardware Design with VHDL Course Introduction ECE 443 Hardware Design with VHDL Instructors:

Hardware Design with VHDL Course Introduction ECE 443 Hardware Design with VHDL Instructors: ECE: Jim Plusquellic FMAC: Craig Kief and Steve Suddarth Text: FPGA Prototyping By VHDL Examples, Xilinx Spartan-3 Version, Pong P. Chu, ISBN:

124 views • 8 slides
VHDL VHDL - Flaxer Eli Ch 2 - 1 Programmable Logic Review (last chapter) VHDL and

VHDL VHDL - Flaxer Eli Ch 2 - 1 Programmable Logic Review (last chapter) VHDL and

Chapter 2 Programmable Logic VHDL VHDL - Flaxer Eli Ch 2 - 1 Programmable Logic Review (last chapter) VHDL and programmable logic = best current solution for rapid design, implementation, testing, and documenting of complex digital

463 views • 11 slides
EITF35: Introduction to Structured VLSI Design Part 2.1.2: VHDL-2 Liang Liu

EITF35: Introduction to Structured VLSI Design Part 2.1.2: VHDL-2 Liang Liu

EITF35: Introduction to Structured VLSI Design Part 2.1.2: VHDL-2 Liang Liu liang.liu@eit.lth.se 1 Lund University / EITF35/ Liang Liu Outline VHDL Objects VHDL Data Types Operators in VHDL Optimizing VHDL Code Operator

907 views • 37 slides
Hardware Design with VHDL Course Introduction ECE 443 Hardware Design with VHDL Instructor:

Hardware Design with VHDL Course Introduction ECE 443 Hardware Design with VHDL Instructor:

Hardware Design with VHDL Course Introduction ECE 443 Hardware Design with VHDL Instructor: Prof. Jim Plusquellic Text: RTL Harware Design Using VHDL: Coding for Efficiency, Portability, and Scalabil- ity, Pong P. Chu, ISBN-13:

482 views • 10 slides
CENG 342 Digital Systems Introduction to VHDL Larry Pyeatt SDSM&amp;T Overview VHDL is a

CENG 342 Digital Systems Introduction to VHDL Larry Pyeatt SDSM&amp;T Overview VHDL is a

CENG 342 Digital Systems Introduction to VHDL Larry Pyeatt SDSM&amp;T Overview VHDL is a popular language for describing digital hardware and widely used by industry worldwide VHDL is an acronym for VHSIC (Very High Speed Integrated

441 views • 10 slides
UMBC A N R Y L D A B M A L F T U M B C I O M 1 (March 29, 1998 4:05 pm) Y O

UMBC A N R Y L D A B M A L F T U M B C I O M 1 (March 29, 1998 4:05 pm) Y O

Principles of VLSI Design VHDL CMSC 491B/711 VHDL Introduction A language for describing the structural, physical and behavioral characteristics of digital systems. Execution of a VHDL program results in a simulation of the digital system.

719 views • 23 slides
VHDL Digital Systems 1 The designers guide to VHDL Peter J. Andersen Morgan Kaufman

VHDL Digital Systems 1 The designers guide to VHDL Peter J. Andersen Morgan Kaufman

VHDL Digital Systems 1 The designers guide to VHDL Peter J. Andersen Morgan Kaufman Publisher Bring laptop with installed Xilinx 2 HDL Introduction VHDL (DoD project) and Verilog (private project) High level languages for

810 views • 62 slides
VHDL Test benches How to simulate VHDL code Use a simulation tool like e.g. ModelSim

VHDL Test benches How to simulate VHDL code Use a simulation tool like e.g. ModelSim

VHDL Test benches How to simulate VHDL code Use a simulation tool like e.g. ModelSim Test bench to apply stimuli/test inputs to the VHDL code Visual inspection through graphical output (waveform) Self checking test

1.1k views • 24 slides
Theorem 7.56 SUBSET-SUM is NP Complete ANSHUMAN MOHANTY SUBSET-SUM Problem Consider a set of

Theorem 7.56 SUBSET-SUM is NP Complete ANSHUMAN MOHANTY SUBSET-SUM Problem Consider a set of

Theorem 7.56 SUBSET-SUM is NP Complete ANSHUMAN MOHANTY SUBSET-SUM Problem Consider a set of numbers S. and a target number t. We have to determine of the exists a subset of S such that the summation of the numbers present in the subset is

353 views • 11 slides
VHDL for Logic Synthesis Overview Design Flow for Hardware Design VHDL coding for

VHDL for Logic Synthesis Overview Design Flow for Hardware Design VHDL coding for

VHDL for Logic Synthesis Overview Design Flow for Hardware Design VHDL coding for synthesis General guidelines for hardware designers This lecture includes the content from: Nitin Yogi, Modelling for Synthesis with VHDL, Auburn

697 views • 52 slides
W4231: Analysis of Algorithms Subset Sum The Subset Sum problem is defined as follows: 11/30/99

W4231: Analysis of Algorithms Subset Sum The Subset Sum problem is defined as follows: 11/30/99

W4231: Analysis of Algorithms Subset Sum The Subset Sum problem is defined as follows: 11/30/99 Given a sequence of integers a 1 , . . . , a n and a parameter k , NP-completeness of Subset Sum, Partition, Minimum Bin Packing. Decide

214 views • 3 slides
Outline 1. Fundamental limitation of EDA software 2. Realization of VHDL operator Synthesis Of

Outline 1. Fundamental limitation of EDA software 2. Realization of VHDL operator Synthesis Of

Outline 1. Fundamental limitation of EDA software 2. Realization of VHDL operator Synthesis Of VHDL Code 3. Realization of VHDL data type 4. VHDL synthesis flow 5. Timing consideration RTL Hardware Design Chapter 6 1 RTL Hardware Design

229 views • 11 slides
Quantum algorithms Subset-sum example: for the subset-sum problem Is there a subsequence of (499

Quantum algorithms Subset-sum example: for the subset-sum problem Is there a subsequence of (499

Quantum algorithms Subset-sum example: for the subset-sum problem Is there a subsequence of (499 852 1927 2535 3596 3608 D. J. Bernstein 4688 5989 6385 7353 7650 9413) University of Illinois at

2.02k views • 163 slides
Approximation Algorithms Subset Sum III Instance : X = { x 1 , . . . , x n } n integer

Approximation Algorithms Subset Sum III Instance : X = { x 1 , . . . , x n } n integer

NEW CS 473: Theory II, Fall 2015 Subset Sum Approximation Algorithms Subset Sum III Instance : X = { x 1 , . . . , x n } n integer positive num- bers, t - target number Question: subset of X s.t. sum of its elements is t ? Lecture 10

200 views • 8 slides
Synthesis Of VHDL Code RTL Hardware Design Chapter 6 1 Outline 1. Fundamental limitation of

Synthesis Of VHDL Code RTL Hardware Design Chapter 6 1 Outline 1. Fundamental limitation of

Synthesis Of VHDL Code RTL Hardware Design Chapter 6 1 Outline 1. Fundamental limitation of EDA software 2. Realization of VHDL operator 3. Realization of VHDL data type 4. VHDL synthesis flow 5. Timing consideration RTL Hardware Design

799 views • 61 slides
More Recursion Summary Topics: more recursion Subset sum: finding if a subset of an

More Recursion Summary Topics: more recursion Subset sum: finding if a subset of an

csci 210: Data Structures More Recursion Summary Topics: more recursion Subset sum: finding if a subset of an array that sum up to a given target Permute: finding all permutations of a given string Subset: finding all

436 views • 15 slides

More recommend