VHDL for Logic Synthesis Overview Design Flow for Hardware Design - PowerPoint PPT Presentation

VHDL for Logic Synthesis

Overview • Design Flow for Hardware Design • VHDL coding for synthesis • General guidelines for hardware designers This lecture includes the content from: Nitin Yogi, Modelling for Synthesis with VHDL, Auburn University Actel HDL Coding Style Guide and other sources 2

System Design Flow Electronic System Level (ESL) flow – System C – TLM, Verification, Profiling -VISTA Mixed-signal Wireless Comm Embedded Computing Architectures Palladium XP HwSw Partitioning – based on MATLAB model - floating point Reconfugurable profiling IP Cores – Internal & Simulink flow MATLAB model - fixed point High Level Synthesis External Software (CtoS, CatapultC, (SystemC, RTL coding (VHDL) flow HandelC) MATLAB, VHDL) RTL coding (VHDL) Verification flow ASIC Logic Synthesis (Synopsys), FPGA LS (Xilinx ISE) -based on system level verification -Assertions and formal ASIC Back-End (CADENCE SE), DfT flow verification actively FPGA P&R (Xilinx ISE) - BIST for memory and used logic -Smart testbenches ASIC DRC & LVS - Scan for logic (Cadence Assura, Polyteda) - FPGA verification - Palladium verification Digital design flow (ASIC; FPGA) 3

VLSI Levels of Abstraction Specification (what the chip does, inputs/outputs) System Level Modeling major resources, connections Register-Transfer logic blocks, FSMs, memory, connections Logic gates, flip-flops, latches, connections Circuit transistors, parasitics, connections Layout mask layers, polygons 4

Activity Flow in Digital Design specifications Functional Design Behavioural description and verification RTL description and RTL Design verification Netlist synthesis and Logic Design simulation Timing Closure Circuit Design Power Analysis Physical Analysis (DRC, Physical Design LVS, ERC) GDS description 5

Applications ASIC Design flow System Specification IP Library HDL RTL Designs IP HDL Top Module Definition Simulation Test Benches no Result OK? no yes yes New synthesis Logic Synthesis Simulation no Result no OK? yes ye New layout run s sufficient? Layout Synthesis Simulation no Result OK? yes 6 Final Chip Layout 6

Design Views and Abstraction Models BEHAVIOURAL STRUCTURAL MPSoC algorithms processors Register transfers registers Signals, expressions gates transistors cells modules chips PHYSICAL • Process of ASIC design starts with behavioral model, goes over structural until physical model 7

VHDL could be applied at multiple levels of abstraction • For detailed view please visit “ Entwurf Digitaler Systeme ” • VHDL can be used to model the circuit of very abstract behavioral level • This description can be refined to the RTL level • Also it can be used for describing the structural netlist After synthesis Cell Delay After layout Cell Delay Interconnect Delay 8

Synthesis Process and different coding Styles • Synthesis converts RTL model to structural model • As a result we get some sort of a netlist (VHDL, Verilog (most frequently), EDIF) Structural model Behavioral (RTL) model architecture netlist of mux is architecture behav of mux is signal CI, D, E:std_logic begin begin Synthesis pr: process(A,B,C) g1: not port map (CI,C); begin g2: and port map (D,A,CI); if (S = '0') then g3: and port map (E,B,C); Y <= A; g4: or port map (Y,D,E); else end; Y <= B; A end if; end process pr; Y C end; B 9

Why we should know the synthesis outcome while describing VHDL? Expected result of synthesis A Behavioral model MUX architecture behav of cont is Out1 B begin p1: process(A,B,C1, C2) C1 begin C2 if (C1 = ‘1') and (C2 = '1') then Out1 <= A; Synthesis elsif (C2 = ‘1') then Out2 <= B; --else we do not care Obtained synthesized design! end if; end process p1; end; A Out1 D Out MUX Latch B EN C1 C2 10

Why is suboptimal design dangerous? • Additional hardware leads to overhead in the area -> additional cost • Additional hardware means additional power consumption -> reduced battery time • Suboptimal design have reduced performances -> longer critical path • Unclarities in the design create potential bugs • (Unintentional) use of latches may lead to problems in timing analysis and glitch generation 11

Why we should know the synthesis outcome while describing VHDL? - Corrected Design Behavioral model architecture behav of cont is begin p1: process(A,B,C1, C2) begin if (C1 = ‘1') and (C2 = '1') then Out1 <= A; Synthesis A elsif (C2 = ‘1') then MUX Out2 <= B; Out1 B else Out2<=‘B’; C1 end if; C2 end process p1; end; Rule of correctly written VHDL: Always define the outputs for all IF cases 12

Typical Digital Circuits • Combinational logic circuits random logic multiplexers Decoders • Arithmetic functions • Sequential logic (registers) synchronous & asynchronous inputs • Shift registers • Finite state machines • Memory synthesis • More advanced circuits (FIFOs, synchronizers, clock gates) 13

How VHDL Simulator works? • VHDL blocks are simulated using event based simulator • Assignments are concurrently executed • Update for all assignments in particular timestamp is performed at the same time • Following assignments (depending on the updates from the previous calculations) are updated with delta cycle delay • Delta cycle delay is simulation quantum time which cannot be visualized, but enables effective execution of events. • When all assignments are eventually resolved (after N delta cycles) the simulator can go to the next timing event in the simulation. X<= Y+ Z; -- assignment executed after delta cycle W<= X-Z; -- after updating the value of X, we will update the value of W as well, -- however with one delta cycle delay compared to the X update Please be careful: A<=B; In this case signals A and B are not identical, and there is a delta delay in between

Variables and Signals • Variables are used only within the process Usually they are utilized for holding the immediate results of the calculation (it is also difficult to visualize them in the simulation) Variables are updated immediately (without delta cycle delay) They enable sequential execution in the process • Signals are always executed with delta delay cycle Behavioral model Behavioral model Behavioral model architecture behav of cont is architecture behav of ex1 is architecture behav of ex2 is begin begin begin p1: process(A,B,C1, C2) p1: process(clk) p1: process(clk) variable Temp:std_logic :=‘0’; --initial value! variable Temp1, variable Temp1, Temp2:std_logic; Temp2:std_logic; begin begin begin if (C1 = ‘1') and (C2 = '1') then if (clk = ‘1') and clk’event then if (clk = ‘1') and clk’event then temp := A; temp1 := A; Out1:=temp2; elsif (C2 = ‘1') then temp2 :=temp1; temp1 := A; temp:= B; Out1:=temp2; temp2 :=temp1; else -- order of operation matters! temp:=‘B’; end if; end if; end if; end process p1; end process p1; Out1<=B; end; end; end process p1; end;

VHDL Coding Styles • Structural • Behavioural • Dataflow architecture netlist of cont is Behavioral model architecture dataflow of cont is signal CI, D, E:std_logic architecture behav of cont is begin begin begin g1: not port map (CI,C); p1: process(A,B,C1, C2) g2: and port map (D,A,CI); begin Out1<=A when C1=‘1’ and g3: and port map (E,B,C); if (C1 = ‘1') and (C2 = C2=‘1’ else B; g4: or port map (Out1,D,E); '1') then end; Out1 <= A; end; else Out2 <= B; end if; end process p1; end;

Sensitivity list in Combinational Logic • All signals affecting results of the combinational process need to be in the sensitivity list • Otherwise the simulation results will not be representative • For synchronous circuits it is only required to have clock (and asynchronous set/reset in the list • Why is this so? Behavioral model architecture behav of cont is begin p1: process(A,B, C2) – missing C1 begin if (C1 = ‘1') and (C2 = '1') then Out1 <= A; else Out2 <= B; end if; end process p1; end; 17

Multiplexer: Using “case” Statement entity Mux4 is port (in1: in std_logic_vector(3 downto 0); s1: in std_logic_vector (1 downto 0); MUX in1 m m: out std_logic); end Mux4; architecture behav of Mux4 is begin S1 process(s1, in1) begin case s1 is when "00" => m <= i(0); when "01" => m <= i(1); when "10" => m <= i(2); when others => m <= i(3); -- why this? end case; end process; end behav; 18

Multiplexer: dataflow implementation entity Mux4 is port (in1: in std_logic_vector(3 downto 0); s1: in std_logic_vector (1 downto 0); MUX in1 m m: out std_logic); end Mux4; architecture behav of Mux4 is begin S1 with s1 select when "00" => m <= i(0); when "01" => m <= i(1); when "10" => m <= i(2); when others => m <= i(3); end behav; This implementation is safer for unexperienced designers => no problems with sensitivity list and complete definition of cases 19