SOI and Related Activities in AGH-UST and IFJ PAN (1) Sebastian Gb , - PowerPoint PPT Presentation

SOI and Related Activities in AGH-UST and IFJ PAN (1) Sebastian Głąb , M.I. Ahmed, Mateusz Baszczyk, Szymon Bugiel, Piotr Dorosz, Roma Dasgupta, Marek Idzik, Wojciech Kucewicz, Jakub Moroń, Maria Sapor (2) Piotr Kapusta, Michał Turała (1) AGH University of Science and Technology, A. Mickiewicza 30, 30-059 Krakow, Poland (2) Institute of Nuclear Physics Polish Academy of Sciences, Radzikowskiego 152, 31-342 Krakow, Poland Email: sglab@agh.edu.pl

Agenda • Presentation of AGH University of Science and Technology; • General description of submitted chips; • First matrix of pixels; • Second matrix of pixels; • Third and fourth matrix of pixels; • Successive Approximation Register Analog-to-Digital Converter; • Bandgap voltage reference with temperature sensor; • Synthesizable digital library. 2

AGH UST history In 1913, Emperor Francis Joseph approved the establishment of a higher school of mining in Krakow. In 1919, Józef Piłsudski, the Head of the State, inaugurated the Academy of Mining. In 1947, an internal resolution was adopted to change the name to the Academy of Mining and Metallurgy. www.agh.edu.pl

Facts and figures • 16 faculties • 57 fields of study • more than 200 specialisations • total number of students: 32,245 full-time students: 26,314 • part-time students: 5,931 • doctoral students: 1002 • postgraduate students: 2284 • • over 170,000 graduates • over 2,000 researchers including 560 independent research workers www.agh.edu.pl

Results of scientific research activity • International projects – nearly 200 • Domestic projects – over 2,000 • Research and innovation: • obtained patents – 93 • patent pending innovations – 112 • Licences: • licence agreements – 39 Publications 5871 Books 141 Chapters in books 479 Articles in magazines 2547 Reports and papers 2425 www.agh.edu.pl

Research and laboratories The supercomputer “Zeus” - classified among 100 most powerful computers in the world The latest generation analytical electron microscope (S)TEM FEI Titan Cubed G-2 60-300 www.agh.edu.pl

Infrastructure Academic Centre of Materials Faculty of Energy and Fuels and Nanotechnology Centre of Computer Science Centre of Ceramics www.agh.edu.pl

Description of submitted chips 8

SOI chips ps submit itted ed by AGH H & IFJ Chip no. 1 (submitted in July 2012): a) One matrix of pixels 32x32 (two layouts: small and large BPW); b) two asynchronous, dynamic logic, 10 bit SAR ADCs; c) bandgap voltage reference and temperature sensor (ver. 1 and ver. 2). 9

SOI chips ps submit itted ed by AGH H & IFJ, cont. Chip no. 2 (submitted in July 2013): a) matrix of pixels 32x32 (two layouts: small and noBPW); b) digital library test structures; c) bandgap voltage reference and temperature sensor (ver. 2b and ver. 3); d) history effect test circuit; e) bare test pixels; f) bandgap diodes test structures; g) SOI2 strip. 10

SOI chips ps submit itted ed by AGH H & IFJ, cont. Chip no. 3 (submitted in July 2014): a) matrix of pixels 16x32 (charge amplifier; small and large BPW); b) matrix of pixels 16x32 (charge amplifier, shaper, peak detector); c) Two asynchronous, static logic, 10 bit SAR ADC; d) bandgap voltage reference and temperature sensor (ver. 4 and ver. 4b). 11

Next MPW submis issi sion on plans ns Chip no. 4 (?April 2015?): a) matrix of self addressing pixels; b) matrix of pixels with Time Over Threshold; c) Improved 10 bit SAR ADC; d) 6 bit, column SAR ADC; e) bandgap voltage reference and temperature sensor (to be decided). 12

Pixel matrices 13

First versi sion on of p pixel Designed by Piotr Kapusta 14

First versi sion on of p pixel, , cont nt. SMALL LARGE 15 Laid by Sebastian Głąb Laid by Piotr Kapusta

First versi sion on of p pixel, l, cont nt. • The measured ENC value was found to be about 115 electrons at 60 V bias and 82 μ s integration time (in which 56 e came from the leakage current, 34 e from the input transistor and the rest, i.e. 94 electrons is produced in the readout electronics (including out of chip components). • The chip operates in the “rolling shutter” mode , the dead time equals 2.7%. • The calculated gain is 9.3ADC units/eV, with non-linearity better than 2.6ADC units. 16 Total Equivalent Noise Charge vs detector bias. Integration time = 90 μ s.

First versi sion on of p pixel, l, cont nt. Am241 spectra from different sensor areas. 17 M. I. Ahmed, S. Głąb, M. Idzik, P. J. Kapusta, M. Turała, Prototype pixel detector in the SOI technology , Journal of Instrumentation; ISSN 1748-0221. - 2014 vol. 9 no. 2, s. 1 – 8 article no. C02010. http://iopscience.iop.org/1748-0221/9/02/C02010

Second ond versi sion on of pixel matrix ix • Circuit schematics same as in first version; • Added SOI2 layer to all pixels; • Large pixels substituted by pixels without BPW area; • One bug fixed (BPW line shorted with bias line); • Broken output amplifier – matrix can not be read… 18

Third ird version ion of p pixel A telescope cascode with an additional current source for higher output resistance. Correlated double sampling. 19 Two different gains. Designed by Szymon Bugiel

New Column mn Amplifier ier 20 Designed by Szymon Bugiel

Third ird version ion of p pixel, l, summary mary • The new pixels use newly designed frontend electronics in the charge amplifier configuration, in order to obtain significantly lower noise level than in the first prototype. • Thanks to use of recycling folded cascode as the column amplifiers a significant reduction of the power consumption should be possible. • Two separate SOI2 areas; one below all PMOS transistors, second one under all NMOS transistors. Possibility to study compensation of radiation damage effects. • Two layouts of pixels: half of the pixels were drawn using standard BPW/BNW layer and other half without it. Possibility to study effectiveness of SOI2 shielding. 21 Szymon Bugiel, Roma Dasgupta, Sebastian Głąb, Marek Idzik, Piotr Kapusta, Development of pixel detector in novel sub-micron technology SOI CMOS 200 nm , MIXDES 2014; proceedings of the 21st international conference; http://ieeexplore.ieee.org/xpl/articleDetails.jsp?reload=true&arnumber=6872186

Fourth rth vers rsion ion of pixel Designed by Piotr Kapusta Details are unknown… 22

3rd and 4th pixel layout outs comparis arison on Designed by Piotr Kapusta Designed by Szymon Bugiel 23

Successive Approximation Register Analog-to-Digital converter 24

10 bit SAR ADC Designed by Roma Dasgupta 25

10 bit SAR ADC, cont. t. Schematics of designed DAC 26 Designed by Roma Dasgupta

10 bit SAR ADC, cont. t. 27 Designed by Roma Dasgupta

10 bit SAR ADC, cont. t. • 10 bit resolution, 20 MSps at a power consumption of about 900 μW . • Zero static power dissipation. • The differential, segmented DAC with merge capacitor switching (MCS) scheme. • The MCS scheme achieves 93.4% less switching energy as compared to the conventional SAR architecture. • Layout size is about 200 μ m × 300 μ m. The dynamic parameters of designed SAR ADC 28 Roma Dasgupta, Szymon Bugiel, Sebastian Głąb, Marek Idzik, Jakub Moroń, Piotr Kapusta, Design and simulations of the 10-bit SAR ADC in novel sub-micron technology 200 nm SOI CMOS , MIXDES 2014; proceedings of the 21st international conference; http://ieeexplore.ieee.org/xpl/articleDetails.jsp?reload=true&arnumber=6872180

Bandgap Voltage Reference and Temperature Sensor 29

Positive ive temperature rature coefficien ficient (PTC TC) It was recognized in 1964 that if two bipolar transistors operate at unequal current densities, then the difference between their base-emitter voltages is directly proportional to the absolute temperature.     kT      V V ln n m ln n m BE th q  V th mV   0 . 087  T K 30

Negative ive temperature rature coefficie icient nt (NTC TC) Forward voltage of p-n junction V BE has negative temperature coefficient.       V 4 m V E / q V  BE th g BE  T T 3   m Temperature exponent of mobility: 2 kT V th  Thermal voltage: q  E g 1 . 12 eV Bandgap energy of silicon: With V BE = 750 mV, T = 300 K:  V BE mV   1 . 5  T K 31

Schemat hematic ic of t the circu cuit it 32

Layout out of the circuit cuit Version 1 and 2 based on „cold” and „hot” diode model respectively. 267 μm x 124 μm (submitted in July 2012) Version 2 with improved layout and version 3. 298 μm x 185 μm (submitted in July 2013) Version 4. 240 μm x 157 μm (submitted in January 2014) Not yet available. 33

Bandgap („hot” diode model) The simulations were done for temperature range from -10 ° C to +130 ° C showing very good temperature sensor linearity and stable (within 1 mV) bandgap voltage output in the whole range. 34