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Future Pixel Detectors Future Pixel Detectors Fermilab 3D and SOI Technology Fermilab 3D and SOI Technology Developments Developments KEK June 25, 2007 Marcel Demarteau For the Fermilab Detector & Physics R&D Group Tsukuba, Japan


  1. Future Pixel Detectors Future Pixel Detectors Fermilab 3D and SOI Technology Fermilab 3D and SOI Technology Developments Developments KEK June 25, 2007 Marcel Demarteau For the Fermilab Detector & Physics R&D Group Tsukuba, Japan June 25, 2007

  2. f Vertex Detectors Vertex Detectors Vertex Pixel detectors are very difficult • Good angular coverage with many layers close to the interaction point – Excellent point resolution (< 4 µ m) – Superb impact parameter resolution ( 5µm ⊕ 10µm/ (p sin 3/ 2 θ ) ) – – Transparency (~ 0.1% X 0 per layer) Robust pattern recognition (track finding in vertex detector alone) – I ntegration over small number of bunch crossings for I LC – < 150 = ~ 50 µ s • Electromagnetic I nterference (EMI ) immunity – Power Constraint (< ~ 100 Watts) with gas cooling – Radiation hard for LHC experiments – • The physics drives the design of HEP pixel electronics and detectors to ever more stringent requirements in all these areas As an example, a pixel detector for the LHC and I LC • Fermilab Pixel Technologies, KEK June 25, 2007 -- M. Demarteau Slide 2

  3. f LHC Pixel Detectors LHC Pixel Detectors All LHC pixel detectors are hybrid pixel detectors: • Separate detector and readout chip, connected by bump bonds sensor and read-out chip (roc) can be – optimized separately I ssues with this technology: • At least twice the mass of the detector since the – readout chip is as thick as the silicon sensor Power consumption in the chip is high – Need active cooling of detectors – Bump bonding is very expensive – CMS Pixel size is too large – CMS pixel size is 100x150 µ m 2 = 15,000 µ m 2 • Atlas pixel size is 50x400 µ m 2 = 20,000 µ m 2 • ILC need ~ 20x20 µ m 2 = 400 µ m 2 • • Area LHC/ILC = 50 Fermilab Pixel Technologies, KEK June 25, 2007 -- M. Demarteau Slide 3

  4. f ILC Pixel Detectors ILC Pixel Detectors • Vertex detector requirements Very low mass: 0.1% X 0 per layer (equivalent of 100 µ m of Si) – • Low mass requires no active cooling, hence low power High resolution: impact parameter resolution of ~ 5 µ m – • Requires smaller pixels which increases the readout circuit density Good and robust pattern recognition, integrated design – • Low occupancies, bunch crossing time stamp – Modest radiation tolerance for I LC applications ~199 ms 969 µ s 969 µ s I LC beam structure • Five trains of 2625 bunches per second – Bunch separation of 369.2 ns – • I LC Maximum hit occupancy Assumed to be 0.03 particles/ crossing/ mm 2 – – Assume 3 pixels hit/ particle (obviously this depends somewhat on pixel size, hit location, and charge spreading) Hit rate = 0.03 part./ bx/ mm 2 x 3 hits/ part. x 2625 bx/ train gives – 252 hits/ train/ mm 2 Fermilab Pixel Technologies, KEK June 25, 2007 -- M. Demarteau Slide 4

  5. f ILC Detector Geometry ILC Detector Geometry At an e + e - linear collider there is a premium on the small angle region • more events are in the forward/ backward regions than in the central – regions • Detector configurations Short barrels with disks – • Barrels: five layers, Longitudinal coverage: ± 62.5 mm, Radial coverage: 14< R< 61 mm • Disks: Four disks, z = ± 72, ± 92, ± 123, ± 172 mm, Radial coverage: R< 71 mm Long barrels, limited disk coverage – Extraction of signals, power distribution, cable plant non-trivial • Fermilab Pixel Technologies, KEK June 25, 2007 -- M. Demarteau Slide 5

  6. f Pixel Detectors Pixel Detectors As mentioned, pixel detectors are very difficult • Many competing requirements – All projects will benefit from advances in any area – New technologies are applicable to many areas of science – • Significant progress has been made to address these issues by integrating sensors and front end electronics within the pixel cell: Monolithic Active Pixel Sensors (MAPS) Fundamental limitations – Pixel control, CDS, • Small signal dependent on epi thickness A/D conversion • Most designs are limited to NMOS transistors • Not 100% fill factor Diode Diode • Slow rise time set by diffusion Fermilab is pursuing alternatives: Analog readout Analog readout • circuitry circuitry A SOI (Silicon On I nsulator) Pixel Sensors – • Offers improvements over MAPS Diode Diode S 3D integrated circuits – Analog readout Analog readout • Also SOI process, but offers improved performance circuitry circuitry over SOI pixel sensors. Conventional MAPS 4 Pixel Layout Fermilab Pixel Technologies, KEK June 25, 2007 -- M. Demarteau Slide 6

  7. f SOI Detector Concept SOI Detector Concept Advantages – 100% fill factor Large and fast signal – Small active volume: high – soft error immunity – Full di-electric isolation: latchup free Low Junction Capacitance: – high speed, low power Bonded Wafer: low resistive top layer + high resistive substrate, separated • through a Buried OXide (BOX) layer Top layer: standard CMOS Electronics (NMOS, PMOS, etc. can be used) – – Bottom substrate layer forms detector volume – The diode implants are formed beneath the BOX and connected by vias Monolithic detector, no bump bonds (lower cost, thin device) • High density and smaller pixel size is possible • Small capacitance of the sense node (high gain V= Q/ C) • I ndustrial standard technology (cost benefit and scalability) • Fermilab Pixel Technologies, KEK June 25, 2007 -- M. Demarteau Slide 7

  8. f Vertical Scale Integrated Circuits (3D) Vertical Scale Integrated Circuits (3D) SOI detector technology offers several advantages over MAPS; 3D offers • advantages over SOI detectors Optical In Optical Out Opto Electronics Power In • A 3D device is a chip comprised of and/or Voltage Regulation 2 or more layers of semiconductor devices which have been thinned, Digital Layer bonded, and interconnected to form Analog Layer 50 um a monolithic circuit Sensor Layer Advantages of 3D over SOI • I ncreased circuit density due to multiple tiers of electronics – I ndependent control of substrate materials for each of the tiers. – Ability to mate various technologies in a monolithic assembly – • Technology driven by industry System on a Chip – Circuit performance limited by interconnects DRAM • Stacked, wirebonded asics Logic – Desire to limit area of active elements MPU Core ROM Provide increased functionality Analog – Cache Reduce interconnect power, crosstalk – Fermilab Pixel Technologies, KEK June 25, 2007 -- M. Demarteau Slide 8

  9. f Benefits of Vertical Integration Benefits of Vertical Integration Many benefits of 3D integration – also for HEP applications • I ntegration of heterogeneous technologies possible – I C fabrication optimized for each functionality reducing cost & increasing yield – • Process optimization for each layer (also called tier) 2-D 3-D – Replaces long horizontal traces with short vertical interconnects A/2 – I nterconnect length decreases therefore Area A R, L, C decreases for higher speed Reduce interconnect power, crosstalk – A/2 – Power, delay and noise reduction Very long wire – Reduce chip I / O pads Short vertical interconnects – Provide increased functionality Pixel control, CDS, A/D conversion Benefits of pixellated arrays • Diode Diode Digital Massively parallel signal – processing Analog readout Analog readout Dramatically increased – circuitry circuitry Analog electronic functionality in each pixel Diode Diode Sensor Analog readout Analog readout circuitry circuitry Conventional MAPS 4 Pixel Layout 3D 4 Pixel Layout Fermilab Pixel Technologies, KEK June 25, 2007 -- M. Demarteau Slide 9

  10. f Key Technologies for 3D Key Technologies for 3D There are 4 key technologies for vertical scale integration • Wafer thinning – • Target thickness < 30 µm • Thickness tolerance = ± 1 µm • Temporary carrier mounting/demounting and thin die singulation without damage to ICs Through-wafer via formation and metallization – • High aspect ratio 3-D interconnects through SiO 2 and Si • Interconnects need to be insulated High precision alignment – • Uniform alignment < ± 1 µm – Bonding between layers • Multiple techniques being employed Many of these technologies are also used in the development of SOI detectors • Fermilab Pixel Technologies, KEK June 25, 2007 -- M. Demarteau Slide 10

  11. f Key Technology: Wafer Thinning Key Technology: Wafer Thinning For compact, low mass devices, layers to be thinned as much as possible • Through-wafer vias typically have an 8 to 1 aspect ratio. I n order to keep • the area associated with the via as small as possible, the wafers should be thinned as much as possible Thinning is typically done by a combination of grinding, lapping, and • chemical or plasma etching Photos from MIT LL Six inch wafer thinned to 6 microns and mounted to 3 mil kapton. Fermilab Pixel Technologies, KEK June 25, 2007 -- M. Demarteau Slide 11

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