Variation is the Future March 17 th 2014 Andrew C. R. Angus 1 , Fikru - PowerPoint PPT Presentation

Statistical Design and Verification of Analogue Systems Variation is the Future March 17 th 2014 Andrew C. R. Angus 1 , Fikru Adamu-Lema 3 , Asen Asenov 34 , Binjie Cheng 4 , Campbell Millar 4 , Neil Munro 2 , Alan Murray 1 , John Pennock 2 , Neil Rankin 2 School of Engineering, University of Edinburgh 1 Wolfson Microelectronics 2 Device Modelling Group, University of Glasgow 3 Gold Standard Simulations (GSS) 4

Statistical Design and Verification of Analogue Systems Contents • Variation in Deep-Submicron CMOS • StatDes • Fabricated Test Chip • Compact Model Extraction • Local Mismatch Plots [Tuinhout CICC13] • Pelgrom Area Scaling • The Future? 17/03/2014 2

Statistical Design and Verification of Analogue Systems Variation in Deep-Submicron CMOS • Industry pressures continue to shrink process nodes  Consumer desires smarter, lower-power devices • Technologies are optimised for the majority (digital) devices  Analogue/Mixed-Signal still crucial for functioning Systems-on-Chip • Active device area is now reaching a point where the discrete nature of charge and matter are noticeably impacting device performance. • Key processing steps are stochastic  intrinsic variation in device performance  overwhelms the contributions of process gradients (small-to-medium devices) • Correct understanding of variability is essential  identify problematic circuit elements  reduce overdesign of circuit blocks where there is no benefit. 17/03/2014 3

Statistical Design and Verification of Analogue Systems Traditional Analogue Solution • Methodology: spend area to mitigate variation  Increasingly costly with each node shrink • Careful layout -> good matching  Consistency of environment  Symmetry  Inter-digitation  Dummy structures • Layout reduces systematic mismatch Symmetrical differential-pair layout with a ring of dummy devices. • Active area reduces intrinsic mismatch • Opportunities for alternatives available (system-level solutions)  Digital sections are cheap  Calibration, reconfiguration and post-processing (digitally assisted analogue). 17/03/2014 4

Statistical Design and Verification of Analogue Systems Intrinsic Variation Sources SANDIA Labs Ohmori, IEDM’08 Inoue ‘09 Line Edge Roughness (LER) Metal Gate Granularity (MGG) Random Dopant Fluctuation (RDF) RDF + LER + MGG LER MGG Atomistic device simulation can help quantify the impact on device performance. 17/03/2014 5

Statistical Design and Verification of Analogue Systems StatDes • A collaborative project between academia and industry to investigate intrinsic variability of deep-submicron devices for analogue circuits. • Primary goal is to verify the compact model extraction and statistical simulation tools developed by academia and show how they can be used to augment the existing tool-chains in use by industry. • Phase One: Test Chip Design and Fabrication (65nm bulk CMOS) • Phase Two: Measurement and Compact Model Extraction • Phase Three: Verification and Statistical Simulation (Current Work) 17/03/2014 6

Statistical Design and Verification of Analogue Systems Fabricated Test Chip Devs. OA Differential pairs OAs Devices n large p n alpha p n • Common 32-pad ring structure used for all modules • 13 modules of devices, differential-pairs and basic Operational Amplifiers:  Devices: 14 per module (common bulk and gate connections)  Diff-pairs: 7 pairs per module (common bulk and gate connections)  Op-Amps: 8 per module (two-stage, Miller compensated) • 78 instances of the test chip were available for measurement using probe- stations at Glasgow and Edinburgh Universities. 17/03/2014 7

Statistical Design and Verification of Analogue Systems Fabricated Test Chip 80µm 150x60nm pch devices • Individual device characterisation is very area intensive • More informative structures: Capacitor  Individual gate connections  Repeated differential-pairs (closer OAs proximity) rather than more dimensions 17/03/2014 8

Statistical Design and Verification of Analogue Systems Compact Model Extraction I-V Device Generative or LUT Mystic characteristic LibraryMaker Model Extraction models device library data RandomSpice Post-processor Statistical Statistical Circuit Simulation Template (supports parallel grid and/or results Simulation Netlist database Results computation option) • GSS Mystic: I-V characteristics -> compact models  Initial nominal extraction requires manual intervention (selection/tuning)  Subsequent fitting of statistical parameters is automated and quick • Constructed device libraries:  Device Look-up Tables (LUTs)  Generative models (derived from parameter distributions) • In this work compact models extracted from device measurements  Alternatively this data could be obtained through atomistic simulation  Individual variation sources  Technologies not yet in production 17/03/2014 9

Statistical Design and Verification of Analogue Systems Compact Model Extraction The result is fitted models accurate across the full operating range of the device. 17/03/2014 10

Statistical Design and Verification of Analogue Systems Statistical Simulation I-V Device Generative or LUT Mystic characteristic LibraryMaker Model Extraction models device library data RandomSpice Post-processor Statistical Statistical Circuit Simulation Template (supports parallel grid and/or results Simulation Netlist database Results computation option) • GSS RandomSpice:  Template netlist driven work-flow (library specific model keywords)  Creates specific netlist instances from LUT or generative models  Simulation performed sequentially or submitted to a compute grid • Data management support:  Potential for vast numbers of data  User-scripted post-processing modules  Backend database storage 17/03/2014 11

Statistical Design and Verification of Analogue Systems Local Mismatch Plots [Tuinhout CICC13 ] 120 Vds=1.2V Drain Current Mismatch Vbs = 0V 100 σ (% Δ Id/ ‹ Id › ) pch 150x60nm 80 nch 150x60nm pch 600x60nm 60 nch 600x60nm 40 Idsat 20 0 0 0.2 0.4 0.6 0.8 1 1.2 Gate Voltage (V) Local mismatch variation plot of drain current against gate voltage for small geometry devices in saturation extracted from differential pair measurements. Useful tool for investigating the impact of parametric gradients on device matching. Tuinhout et al have found that careful attention to the layout is more important for matching than keeping a short distance between the components. 17/03/2014 12

Statistical Design and Verification of Analogue Systems Pelgrom Area Scaling 12 Vgs =Vds=1.2V Drain Current Mismatch %Id pch Vbs = 0V 10 %Id nch 150x60nm yn = 0.9291x σ (% Δ Id/ ‹ Id › ) %Id nch meas 8 Linear (%Id pch) Linear (%Id nch) 6 yp = 0.7485x 600x600nm 4 2 0 0 2 4 6 8 10 12 (WL)^-0.5 (µm -1 ) Pelgrom plot of drain current mismatch for eight device geometries. Area scaling continues to be applicable with a slightly better per area matching of pch devices. 17/03/2014 13

Statistical Design and Verification of Analogue Systems The Future? • Current CAD/EDA tools generally support the use of statistical models and simulation of circuit designs to verify their behaviour. • This provides necessary confidence that a circuit block will yield correctly when manufactured • However, on its own this does not provide insight into what elements are sensitive to variation or should be modified to reduce overdesign. • Tools should further support statistical analysis and data mining of simulation results  augment designer expertise  allow for a rapid exploration of the design space  ensure variation-awareness from the initial nominal design. 17/03/2014 14

Statistical Design and Verification of Analogue Systems Questions? 17/03/2014 15