Untethering the Rocket-Chip Producing a stand-alone lowRISC SoC Wei Song 07/10/2015 1
Background • Rocket-chip – An open-source SoC from UC Berkeley – Rocket core • RISC-V 64 ISA • 5/6 stage single-issue in-order processor • Non-blocking L1 D$ • Performance comparable to ARM Cortex-A5 • Chisel (RTL, OO, functional) • Zynq FPGA (ARM A9), Linux bootable • Full cross-compilation tool chain 2
Rocket-Chip Rocket Tile Rocket Tile Rocket Tile UART Rocket Rocket Rocket Core Core Core Host ARM SD Interface I$ D$ I$ D$ I$ D$ EtherNet L2 Bus Cached TileLink L2 & L2 & L2 & Uncached TileLink Coherence Coherence Coherence Manager Manager Manager AXI MemIO Arbiter Issues: TileLink/AXI 1. Must work with a companion core (ARM). AXI Bus 2. No direct IO (peripheral) support. 3. No direct bootloading. AXI/MemIO Memory Controller 3
lowRISC-Chip Cached TileLink Rocket Tile Rocket Tile Rocket Tile Uncached TileLink Rocket Rocket Rocket Core Core Core AXI I$ D$ I$ D$ I$ D$ AXI-Lite Uncached TileLink for MMIO L2 Cache Bus L2 IO Bus L2 & L2 & L2 & Chisel TileLink/AXI-Lite Coherence Coherence Coherence Manager Manager Manager SystemVerilog Arbiter Boot Minion coherent Tag Cache DMA DMA UART SD incoherent TileLink/AXI AXI Bus On-FPGA Memory Boot Ram Controller 4
Memory Mapped IO (1) mem.req mem.grant mshrs mshr mshrs.meta_write mshrs.request mshrs.replay s2_hit s2_req Arbiter s1_req s1_req.addr dtlb s1_addr s2_hit vpn meta meta ppn Arbiter s1_addr read resp write cpu.req = = = = data amoalu data Arb s1_tag_eq_way write Arbiter rhs out s2_data read resp lhs s1_data Stage 1 Stage 2 Stage 4 Stage 3 cpu.resp EX MEM WB 5
Memory Mapped IO (2) mem.grant io.grant mem.req io.req mshr mshrs mshrs.meta_write mshrs.request mshrs.replay iomshr iomshr.replay replay io_data io_data s1_io_data request s2_hit s2_req ioaddr Arbiter s1_req addr io s2_req.addr s1_req.addr dtlb s1_addr s2_io_replay vpn s2_io_data meta meta ppn Arbiter s1_addr read resp write cpu.req = = = = data amoalu data s1_tag_eq_way Arb write Arbiter rhs out s2_data read resp lhs s1_data Stage 1 Stage 2 Stage 4 Stage 3 6 cpu.resp
Bootloading Procedure (1) Rocket Tile Rocket Tile Rocket Tile Memory: 0x00000000 – 0x3FFFFFFF Rocket Rocket Rocket IO space: 0x40000000 – 0xFFFFFFFF Core Core Core DDR3 memory in IO space (bypass L1/L2) I$ D$ I$ D$ I$ D$ Uncached TileLink for MMIO L2 Cache Bus L2 IO Bus L2 & L2 & L2 & Chisel TileLink/AXI-Lite Coherence Coherence Coherence SystemVerilog Manager Manager Manager 0x80000000 Arbiter Boot Minion coherent Tag Cache DMA UART SD DMA incoherent TileLink/AXI Linux image AXI Bus 0x00000000 0x40000000 On-FPGA Memory Copy Linux image from SD to DDR3 Boot Ram Controller using IO space (bypassing L1/L2). Bootloader 7
Bootloading Procedure (2) Memory: 0x40000000 – 0x7FFFFFFF -> Rocket Tile Rocket Tile Rocket Tile 0x00000000 – 0x3FFFFFFF Rocket Rocket Rocket Core Core Core IO space: 0x80000000 – 0xFFFFFFFF I$ D$ I$ D$ I$ D$ DDR3 memory in memory space Uncached TileLink for MMIO L2 Cache Bus L2 IO Bus L2 & L2 & L2 & Chisel TileLink/AXI-Lite Coherence Coherence Coherence SystemVerilog Manager Manager Manager 0x80000000 Arbiter Boot Minion coherent Tag Cache DMA UART SD DMA incoherent TileLink/AXI Linux image AXI Bus 0x00000000 0x40000000 Remap DDR3 to Memory 0x00000000 – 0x3FFFFFFF On-FPGA Memory Boot Ram Controller Reset L1/L2 (clean any instructions from bootlaoder) All must be coded in one cache line (16 insns) Linux image Bootloader 8
Bootloading Procedure (3) Memory: 0x40000000 – 0x7FFFFFFF -> Rocket Tile Rocket Tile Rocket Tile 0x00000000 – 0x3FFFFFFF Rocket Rocket Rocket Core Core Core IO space: 0x80000000 – 0xFFFFFFFF I$ D$ I$ D$ I$ D$ DDR3 memory in memory space Uncached TileLink for MMIO L2 Cache Bus L2 IO Bus L2 & L2 & L2 & Chisel TileLink/AXI-Lite Coherence Coherence Coherence SystemVerilog Manager Manager Manager 0x80000000 Arbiter Boot Minion coherent Tag Cache DMA UART SD DMA incoherent TileLink/AXI Linux image AXI Bus 0x00000000 0x40000000 On-FPGA Memory Boot Ram Controller Linux image Bootloader 9
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