Tutorial on Design For Manufacturability for Physical Design - PowerPoint PPT Presentation

Tutorial on Design For Manufacturability for Physical Design Andrzej J. Strojwas PDF Solutions Inc., San Jose, CA & Carnegie Mellon University, Pittsburgh, PA 2005 ISPD, San Francisco, CA April 5, 2005

Overview of Presentation � Yield Loss Mechanism Evolution � Classification of DFM Approaches � True DFM: Defining Proactive DFM � Necessary Conditions for Proactive DFM � Process Characterization � Design Flows that Provide Proactive DFM � DFM Results � Looking into the Future: Extreme Layout Regularity Yield, Performance, Profitability

The Evolution of Product Yields Yield Limiters by Technology Node 100% 90% 80% Yield 70% 60% Random Defect Limited Yield Design Feature Limited Yield 50% Total Yield 40% m m m m m m m u u u u n u u 0 8 5 5 5 8 3 . . 3 2 1 1 9 0 0 . . . . 0 0 0 0 Technology � Random defects are no longer the dominant yield loss mechanism • Yields are limited by design features, systematic and parametric effects Yield, Performance, Profitability

Random Yield Loss Mechanisms – Al Interconnect Material opens Material shorts Type Yield Loss Mechanisms Random Active, poly and metal shorts and opens due to particle defects Contact and via opens due to formation defectivity Yield, Performance, Profitability

Systematic Yield Loss Mechanisms - Cu Interconnect Sparse neighborhood Failure Rate 160 Via Failure Rate (fpb) 140 120 100 80 60 40 20 0 0.4 1.8 4.2 9 Pitch (um) Type Yield Loss Mechanisms Systematic Impact of micro/macro loading design rule marginalities Leakage from STI related stress Contact/via opens due to local neighborhood effects (e.g. pitch/hole size) Misalignment, line-ends/borders Yield, Performance, Profitability

Systematic Yield Loss: Printability – Nanometer Era Type Yield Loss Mechanisms Systematic Poor contact coverage due to misalignment and defocus/pull back Poly/Metal shorts Material opens Yield, Performance, Profitability

Parametric Yield Loss Mechanisms – Nanometer Era Environment dependent poly CD variation ACLV / CD Variation -6.00 -6.50 Env I Env II Env III -7.00 -7.50 -8.00 Ioff -8.50 -9.00 -9.50 -10.00 -10.50 300.00 400.00 500.00 600.00 700.00 800.00 Idrive Type Yield Loss Mechanisms Parametric Performance variation from lithography effects e.g., contact/via coverage, active/poly flaring, CD variation Dummy fill parasitic effects Device mismatch Non-physical corner modeling Yield, Performance, Profitability

Technology Challenges: Implications for Manufacturability 45nm 45nm 65nm 65nm 90nm 90nm � Litho: � Litho: � Litho: � Litho: � Layout pattern � Back-end integration � Layout pattern � Back-end integration � OPC/PSM integration � OPC/PSM integration dependence, Scanner NA, issues dependence, Scanner NA, issues issues w/photo window issues w/photo window � Low k: stress and Immersion litho, OPC/PSM � Low k: stress and Immersion litho, OPC/PSM (DOF) (DOF) integration, issues w/photo reliability integration, issues w/photo reliability � Front-end/Transistor � Front-end/Transistor � CMP - multi-layer � CMP - multi-layer window (DOF) window (DOF) � Layout dependent � Layout dependent � Front end/Transistor � Front end/Transistor topography issues topography issues performance performance � New transistor � Product ramp issues � New transistor � Product ramp issues � Product ramp issues � Product ramp issues � Variability architectures (UTB, DG SOI) � Variability architectures (UTB, DG SOI) � Parametric variations - � Parametric variations - � Product ramp issues � Yield-performance � Product ramp issues � Yield-performance > yield loss > yield loss � Reliability assurance � Reliability assurance tradeoffs tradeoffs Yield, Performance, Profitability

DFM is a Business Opportunity "Seamless" DFM Can Contribute 5% More Good Die What's 5% more good die worth? � $50M over the life of a cell phone � $80M over the life of a game chip � $100M per year per fab at 90nm Yield, Performance, Profitability

A Brief History of DFM Functional Yield means Rules Performance Yield is Covered by Corners Idsat Distribution -200 600 650 700 750 800 850 900 950 1000 1050 -250 ASIC Corners -300 PIdsat -350 Realistic Corners -400 -450 -500 NIdsat � The corners represent the process � Design rules guarantee � …The corners don’t represent the yield!…well, not really… process but they are conservative � …then recommended rules � …Within chip variations are � …and opportunistic design important so.. data base post-processing to • Restrict transistor layouts? enforce them • Statistical timing simulation? Yield, Performance, Profitability

Proactive DFM � Designer access to the Design Verification and Yield Opt. Manufacturing Design Verification and Yield Opt. Manufacturing process is limited MDP Timing Dummy Fill and � Most DFM today is Reactive Physical Mask IP lib. and SI and Volume • Increase in design cycle time Verification Design Analyses Cheesing Making Production • Misaligned mask GDSII and design database OPC/ Yield Physical Post-GDS • Risky design feature changes pre-MDP RET Ramp SP&R Yield Opt. � DFM needs to be Proactive Design Verification and Yield Opt. Manufacturing Design Verification and Yield Opt. Manufacturing � Occurring early in the design MDP and flow Timing Dummy Fill Physical Mask and SI and IP lib. Volume � Up-front accurate process Verification Making Analyses Cheesing Design Production characterization � Yield modeling to characterize IP and drive OPC/ Yield Physical Post-GDS pre-MDP RET Ramp SP&R Yield Opt. EDA tools Process Characterization + Yield Modeling Yield, Performance, Profitability

Necessary Conditions for Pro-Active DFM � Accurate characterization of design-interactions at target fab(s) � Effects modeled across the whole process window � Quantification of alternatives that allow EDA tools to make millions of DFM trade-offs � Integration early in the design flow where there are more degrees of freedom • Floor planning • SP&R � Modifications made prior to verification Yield, Performance, Profitability

Yield Simulation is Core to Proactive DFM Yield Simulation allows for better understanding of the DFM universe � A yield model for DFM: • Model of failure rate of a design element (e.g., transistor, contact, via) as a function of the layout design • Example: • What is the failure rate of a single via vs. double? • What is the probability of a short in two metal lines if there are lots of vias underneath them � To do this, we need process characterization Yield, Performance, Profitability

Process Yield Loss Mechanisms Mx V2 V2 Yield Loss Mechanisms Yield Loss Mechanisms M2 M2 • Layer defect densities • Attribute dependent failure rates V1 V1 • Lithography / CMP driven interactions M1 M1 • … C C Poly Poly Active � Yield Loss Mechanisms ( � Yield Loss Mechanisms (YLM’s YLM’s) ) • Root causes of process related yield loss • Each YLM must be characterized in the process with a specific test structure – Characterization Vehicle (CV) Yield, Performance, Profitability

Typical Die Yield Estimation − Die Yield Model = D A Y e 0 100% Area = 2 cm^2 Area = 1.5 cm^2 where , 80% Area = 1 cm^2 Die Yield = Area = 0.5 cm^2 Y die yield 60% = 2 40% D mean defects (1/cm ) 0 = 20% 2 A die area (cm ) 0% 0 0.5 1 1.5 2 Mean Defectivity (1/cm^2) � Model implies that for a given die size, yield is based only upon process maturity – this is not correct • Yield is different for different IP content • Process defectivity is different for each module Yield, Performance, Profitability

Process-Design Interaction Ratio << 1.0 Ratio >> 1.0 Ratio << 1.0 Ratio >> 1.0 Die Content Impact on Yield Memory (~40mm^2 Die Size) 55% Memory Total Yield (130nm) Total Yield (90nm) 45% Logic Yield 35% Logic 25% Y = 15% Y MEMORY Y LOGIC 5% 0.0 1.0 2.0 3.0 4.0 Memory/Logic Ratio � Chip Yield is a strong function of design content • Physical design features interact with specific module weakness Yield, Performance, Profitability

Accurate Process Characterization Metal Opens/Shorts Metal Opens/Shorts Defect Size Distribution by Characterization Vehicle Characterization Vehicle Process Module Defect Density [Defects/cm^2] Poly and Active Opens/Shorts Poly and Active Opens/Shorts Characterization Vehicle Characterization Vehicle Defect Size [um] DSD(x) = defect size/coun t distributi on Yield, Performance, Profitability

Product Design Attributes I/O Design Attributes Design Attributes ROM • Widths, lengths and spacing SRAM • Counts • Densities • Overlaps/enclosures Custom • … Logic ASIC Logic Analog � Design Attributes: Design Attributes: • Physical design properties that interact with specific module marginalities • Each attribute can be extracted from physical layout • Design attribute extraction (DAE) enables quantification of design content specific YLM models Yield, Performance, Profitability