Total current collapse in High Voltage GaN MIS HEMTs induced by - PowerPoint PPT Presentation

Total current collapse in High ‐ Voltage GaN MIS ‐ HEMTs induced by Zener trapping Donghyun Jin, J. Joh*, S. Krishnan*, N. Tipirneni*, S. Pendharkar* and J. A. del Alamo * Acknowledgement: SRC, ARPA-E, Samsung Fellowship 1

Current collapse or dynamic ON ‐ resistance in GaN FETs • R ON depends on device history  After high V OFF , R ON ↑↑ • Big problem in power switching applications 2

Multi field ‐ plate (FP) technology FP3 Non ‐ FP FP1 FP2 Multi ‐ FP G G D D AlGaN AlGaN GaN GaN • Key challenge for current collapse ↓↓ : Engineering electric ‐ field profile at high ‐ V in the gate ‐ to ‐ drain gap of GaN MIS ‐ HEMTs (Metal ‐ Insulator ‐ Semiconductor High ‐ Electron ‐ Mobility Transistors) → Mul � fi eld ‐ plate technology developed 3

Multi field ‐ plate (FP) technology FP3 Non ‐ FP FP1 FP2 Multi ‐ FP V G < V T G G High ‐ V D D AlGaN AlGaN GaN GaN E ‐ field • In high ‐ V OFF ‐ state, Non ‐ FP → intense E ‐ fi eld peak → current collapse ↑↑ 4

Multi field ‐ plate (FP) technology FP3 Non ‐ FP FP1 FP2 Multi ‐ FP V G < V T G G High ‐ V D V G < V T D High ‐ V AlGaN AlGaN GaN GaN E ‐ field E ‐ field • In high ‐ V OFF ‐ state, Non ‐ FP → intense E ‐ fi eld peak → current collapse ↑↑ Multi ‐ FP → depletion region extension and E ‐ fi eld peak ↓↓ → Effectiveness in current collapse? 5

Current collapse at high V OFF GaN MIS ‐ HEMTs with multi ‐ FP (FP1,2,3): • OFF ‐ state step ‐ stress with V DS ↑ • Monitor I Dlin (equivalent to R ON ) I Dlin (V GS = 0 V, V DS = 0.2 V) V DS … 0.2 V t OFF ‐ state stress characterization V GS t 0 V … V T – 5 V 10 s at every step 6

Current collapse at high V OFF GaN MIS ‐ HEMTs with multi ‐ FP (FP1,2,3): • OFF ‐ state step ‐ stress with V DS ↑ Current collapse • Monitor I Dlin (equivalent to R ON ) 1 V GS = V T – 5 V 0.8 I Dlin (V GS = 0 V, V DS = 0.2 V) I Dlin/ I Dlin (0) 0.6 V DS 0.4 … 0.2 R ON /R ON (0) >10 10 0.2 V t 0 OFF ‐ state stress 0 200 400 600 800 characterization V GS V DS_STRESS (V) t 0 V … • Total current collapse for V DS > 300 V V T – 5 V • R ON ↑↑ by > 10 10 by V DS = 720 V 10 s at every step 7

Questions to answer • Is current collapse recoverable? • Where in the device does this happen? • What are the dynamics of this process? • What is the mechanism responsible? • How to mitigate/eliminate? 8

Current collapse recovery? • 6 consecutive measurements • UV exposure + thermal treatment (180 min at 200 o C) in between 1 OFF ‐ state stress: V GS =V T ‐ 5 V 0.8 2 nd I Dlin /I Dlin (0) 3 rd 0.6 1 st run 4 th 0.4 5 th 6 th 0.2 0 0 100 200 300 400 V DS_STRESS (V) Current collapse fully recoverable  trapping! 9

Lateral extent of current blockage? Change in output characteristics after V DS =300 V stress for 300 s: 600 V GS –V T = 7 V 5 V 3 V Virgin 14 After STRESS 500 12 I D (mA/mm) V GS –V T = 7 V 400 I D (mA/mm) 10 5 V 1 V 8 300 6 3 V 200 After 300 V 4 STRESS 1 V 100 2 -1V 0 0 0 3 6 9 12 15 0 3 6 9 12 15 V DS (V) V DS (V) Current collapse for low V DS but I D flows again at high V DS  punchthrough ‐ like characteristics  current blockage is short along channel direction 10

Change in V T and terminal currents? Evolution of subthreshold characteristics and 4 terminal currents: 1.E+02 Virgin 100 V 1.E+02 V DS = 0.25 V 200 V 1.E+01 I STRESS (nA/mm) 1.E+00 I D 300 V I D (mA/mm) 1.E+00 1.E-02 360 V |I B | V T0 1.E-01 1.E-04 |I S | 400 V 1.E-02 1.E-06 500 V 1.E-03 |I G | 1.E-08 1.E-04 1.E-10 0 100 200 300 400 -9.25 -2 -7.25 0 -5.25 2 -3.25 4 -1.25 6 V DS_STRESS (V) V GS -V T0 (V) • No change in V T  current blockage in extrinsic device region • At the onset of severe trapping, all currents are negligible 11

Impact of device geometry? 1 1 L GD L FP1 longer FP1 0.8 0.8 standard I Dlin /I Dlin (0) I Dlin /I Dlin (0) standard 0.6 0.6 long long 0.4 short 0.4 short 0.2 0.2 0 0 0 100 200 300 400 0 100 200 300 400 (a) (b) V DS_STRESS (V) V DS_STRESS (V) 1 1 L FP2 L FP3 FP2 FP3 0.8 0.8 standard I Dlin /I Dlin (0) I Dlin /I Dlin (0) long 0.6 0.6 short long 0.4 0.4 standard short 0.2 0.2 0 0 0 100 200 300 400 0 100 200 300 400 (d) (c) V DS_STRESS (V) V DS_STRESS (V) Current collapse independent of L GD and geometry of field ‐ plates 12

Current blockage location? Capacitance ‐ voltage characteristics of virgin device: FP1 1 V GS = V T – 5 V 0.8 C DG /C DG (0) FP2 0.6 0.4 FP3 0.2 0 0 100 200 300 400 V DS (V) Channel under field plates fully depleted by V DS =50 V  For V DS >50 V, electric field peaks in channel under edge of FP3  Current blockage under edge of FP3 13

Role of temperature? OFF ‐ state step ‐ stress at different T: 1 1.E+00 1.E+00 I D I G I D ( μ A/mm) 200 °C 1.E-01 0.9 V GS = V T – 5 V 1.E-01 100°C I G ( μ A/mm) 1.E-02 1.E-02 0.8 100 °C 200 °C 1.E-03 I Dlin /I Dlin (0) 1.E-03 0.7 100 °C 25 °C 1.E-04 1.E-04 25 °C 0.6 1.E-05 1.E-05 25°C 0.5 1.E-06 1.E-06 0.4 0 100 200 300 400 1.E+00 0 100 200 300 400 1.E+00 200 °C I S I B 200°C VDS_STRESS (V) 1.E-01 0.3 1.E-01 VDS_STRESS (V) I S ( μ A/mm) I B ( μ A/mm) 200 °C 100 °C 1.E-02 1.E-02 0.2 1.E-03 100 °C 1.E-03 0.1 1.E-04 25 °C 1.E-04 0 1.E-05 1.E-05 25 °C 0 100 200 300 400 1.E-06 1.E-06 0 100 200 300 400 V DS_STRESS (V) 0 100 200 300 400 (a) (b) V DS_STRESS (V) V DS_STRESS (V) • Terminal currents ↑↑ as T ↑  Not source of trapping • Total current collapse independent of T  Trapping through tunneling process 14

Dynamics of trapping Zener tunneling law: Evolution of I Dlin during trapping process: � � � ln τ � � �� � �� � � � � 1 � ���� V GS = V T – 5 V 1000 0.8 I Dlin /I Dlin (0)  0.6 100 τ (sec) 0.4 140 V 160 V 150 V 10 170 V 0.2 E T – E V ≈ 1 eV 180 V 0 1 0 4 8 10 2 6 0 2 4 6 8 10 0.3 0.32 0.34 0.36 Time (min) 1/E PEAK (cm/MV) • Trapping accelerated as V DS_stress ↑ • Characteristic trapping time exhibits Zener ‐ like dependence on peak electric field under FP3 edge (from simulations) 15

Dynamics of thermal detrapping Evolution of I Dlin during detrapping at different temperatures: OFF ‐ state stress: V DS_stress = 200 V, t= 600 sec 18.5 18 ln(T 2 t) (K 2 s) 17.5 17 E A = 0.63 eV 16.5 16 24 26 28 30 1/kT (eV -1 ) • Detrapping accelerated as T ↑ • Activation energy: E A = 0.63 eV 16

Dynamics of UV ‐ enhanced detrapping Evolution of I Dlin during detrapping under UV exposure (300K): OFF ‐ state stress: Stress Recovery V DS_stress =300 V, t=3 min 3.5 eV 1 0.8 4.1 eV I Dlin /I Dlin (0) 0.6 3.1 eV 0.4 0.2 2.8 eV 0 Dark 0 5 10 15 20 Time (min) Detrapping accelerated by UV with E h  > 2.8 eV 17

Electric field simulations Silvaco simulations of electric field at top surface of AlGaN barrier from gate to drain: V GS = V T – 5 V 7 E PEAK 7 6 E PEAK (MV/cm) 6 E-field (MV/cm) 5 5 4 4 3 1000 V 3 2 800 V 2 600 V 1 1 400 V 100 V 0 200 V 0 0 200 400 600 800 1000 Gate FP1 FP2 FP3 4 9 14 19 V DS (V) Space • In OFF ‐ state for V DS > 100 V, field peaks under edge of FP3 • E PEAK increases with V DS • At V DS =200 V, E PEAK = 3.4 MV/cm 18

Summary of key findings • Total current collapse after high V OFF bias: – Fully recoverable – Triggered and accelerated by electric field – Follows Zener ‐ like dependence with E T –E V = 1.0 eV – Trapped region very short and located under FP3 edge – No effect from variations of L GD and FPs lengths – Temperature independent trapping process – Detrapping enhanced by UV with E h  > 2.8 eV – Detrapping enhanced by temperature with E A = 0.63 eV 19

Mechanism for total current collapse Observations consistent with: • Field ‐ induced trapping process  Zener trapping • Takes place in narrow region under edge of FP3 • Electrons from valence band tunnel to traps • Trapped electrons lift bands in ON state and create blockage At high ‐ V OFF After high ‐ V OFF 20

Energy location of traps? • From Zener trapping calculations: E T ‐ E V ≈ 1.0 eV • From UV detrapping experiments: E h  ≈ 2.8 eV • For reference: E g (GaN) = 3.4 eV, E g (Al 0.2 Ga 0.8 N) = 3.8 eV 21

Thermal detrapping with E A =0.63 eV? Thermal detrapping E a =0.63 eV seems inconsistent with energy picture… If blockage region is short, thermal detrapping possible with E < E C ‐ E T 22

Physical origin of traps? • Trap energy consistent with traps responsible for yellow luminescence in AlGaN and GaN. • In GaN: E C ‐ E YB = 2.5 eV (Calleja, PRB 1997) • In Al 0.2 Ga 0.8 N: E C ‐ E YB = 2.8 eV (Hang, JAP 2001) • Yellow luminescence traps attributed to C in N site (Lyons, APL 2010) Mitigation: carefully manage C doping in buffer and migration to AlGaN barrier 23