TOS for the Raspberry Pi Yeqing Yan Abhijit Parate Anoja Rajalakshmi Arno Puder Overview: ● Hardware Architecture of the Raspberry Pi ● ARM Assembly ● Boot Sequence ● Context Switch ● Exception Handling ● Framebuffer 1
Raspberry Pi Overview • Credit card sized computer developed by Raspberry Pi Foundation. • Developed to promote teaching of basic computer science. • Its very low cost ($25) and low powered. • It comes with Broadcom SoC (System-on-Chip) which includes an ARM CPU and a GPU. • 256MB to 1GB RAM. • SD card to store the OS and other data. • Few connectors to connect external devices including Internet. • Homepage: https://www.raspberrypi.org/ 2
Inputs & Outputs • 10/100 Mbit/s Ethernet port (RJ45) • 2 x USB (I/O) • HDMI 1.4 - Audio and Video (O) • Composite Video (O) • 3.5mm Audio connector (O) • 15 MIPI Camera Interface (I) These are compact and low cost solutions developed • DSI (Display Serial Interface) (O) for mobile devices by MIPI Alliance. • Onboard Integrated Interchip Sound (I) • 17 GPIO Pins (8 General & others multifunctionals) (I/O) 3
4
5
Models 1 Gen Model 2nd Gen ZERO 3rd Gen A A+ B B+ Year 2013 2014 2012 2015 2015 2015 2016 Cost $25 $20 $35 $25 $35 $5 $35 SoC BCM2835 BCM2836 BCM2835 BCM2837 CPU ARM1176JZF-S @700MHz Cortex-A7 ARM1176JZF-S ARM Cortex-A53 @1.0GHz @900MHz @1.2GHz RAM 256 MB 512 MB 1 GB 512 MB 1 GB GPU Broadcom VideoCore IV Others 1 USB 2 USB 4 USB I Micro USB 4 USB Ethernet Ethernet Ethernet 46 GPIO Wifi 802.11n 8 GPIO 17 GPIO 17 GPIO Bluetooth 4.1 17 GPIO 6
Model B Specs SOC : Broadcom BCM 2835 CPU : 700 MHz Single-core GPU : Broadcom VideoCore IV @ 250 MHz RAM : 512 MB Storage : SD card up to 512GB Video Out: HDMI and Composite out | In : 15 pin MIPI Camera Interface Audio Out: 3.5 mm jack | In : IIS pins Other connections Ethernet 10/100 Mbits/s (RJ45) 17 GPIO Pins 7
SoC Architecture (Model B) 8
What is ARM? ARM, originally Acorn RISC Machine, later Advanced RISC Machine ● It is a family of reduced instruction set computing (RISC) architectures for computer processors, configured ● for various environments British company ARM Holdings develops the architecture and licenses it to other companies, who design ● their own products that implement one of those architectures— including systems-on-chips (SoC) that incorporate memory, interfaces, radios, etc. It also designs cores that implement this instruction set and licenses these designs to a number of ● companies that incorporate those core designs into their own products. ARM Holdings provides to all licensees an integratable hardware description of the ARM core as well as ● complete software development toolset (compiler, debugger, software development kit) and the right to sell manufactured silicon containing the ARM CPU. For example, Raspberry Pi has Broadcom BCM2835 SoC architecture with ARMv6 architecture. ● The ARM architectures used in smartphones, PDAs and other mobile devices range from ARMv5 to ARMv6 ● ARM Holdings' primary business is selling IP cores, which licensees use to create micro controllers (MCUs), ● CPUs, and systems-on-chips based on those cores.
History of ARM Architecture Version Year Features Implementation v1 1985 The first Commercial RISC (26-bit) ARM1 v2 1987 Coprocessor support ARM2, ARM3 v3 1992 32-bit, MMU, 64-bit MAC ARM6, ARM7 v4 1996 Thumb ARM7TDMI, ARM8, ARM9TDMI, StrongARM v5 1999 DSP and Jazelle extensions ARM10, XScale v6 2001 SIMD, Thumb-2, ARM M0,M0+,M1 multiprocessing ARM11, ARM11 MPCore v7 2006 Thumb, Thumb-2,32-bit, MPU,DSP, Integrated Sleep modes, 6 ARM Cortex M3,M4,M7 stage pipelining, v8 2014 64-bit, advanced SIMD,Hardware Visualization Support ARM Cortex-A32 to 73
Processor Operating Modes User Mode Restricted access to special registers and other protected resources FIRQ Fast Interrupt Mode IRQ * Interrupt (Regular) Mode Supervisor Full control of hardware Abort On failure to load instructions or data from memory Undefined Instruction is undefined System * Same degree of privilege as supervisor mode 11 * = Used in TOS
Processor Operating Modes • User mode: Program being executed is unable to access some protected system resources or to change mode, other than by causing an exception to occur. • The modes other than User mode are known as privileged modes, five of them are known as exception modes, they are entered when specific exceptions occur. • FIQ (Fast Interrupt) • IRQ (Regular Interrupt) • Supervisor • Abort • Undefined • System mode is a privileged mode which is not entered by any exception and has exactly the same registers available as User mode, but it not subject to the User mode restrictions. • The operating modes are controlled by using mode control bits from CPSR (see later slides) 12
Registers • The ARM processor has a total of 37 registers • 31 general-purpose registers, including a program counter (PC) are 32 bits wide. • 6 status registers. These registers are also 32 bits wide. • Registers are arranged in partially overlapping banks, with the current processor mode controlling which bank is available. At any time, 15 general-purpose registers (R0 to R14), one or two status registers (CPSR or SPSR), and the program counter (R15, also called PC) are visible. • The general-purpose registers R0 to R15 can be split into three groups. • These groups differ in the way they are banked and in their special-purpose uses: • The unbanked registers, R0 to R7 • The banked registers, R8 to R14 • Register 15, the PC 13
General Purpose Registers SP - Stack pointer LR - Link register PC - Program counter • 64 byte register bank R14 (LR) R15 (PC) • 16 registers x 32-bit each • Can be used as 32 floating point registers R12 R13 (SP) • R15 Program Counter R10 R11 • R14 Link Register • R13 Stack Pointer R8 R9 • R12 Intra-Procedural scratch register R6 R7 • R0 to R11 are truly general purpose registers R4 R5 R2 R3 R0 R1 14
General Purpose Registers R0 R0 R0 R0 R0 R0 � � � � � � � � � � � � R8 R8 FIQ R8 R8 R8 R8 � � � � � � � � � � � � R13 R13 FIQ R13 IRQ R13 SVC R13 ABT R13 UND R14 R14 FIQ R14 IRQ R14 SVC R14 ABT R14 UND R15 R15 R15 R15 R15 R15 CPSR CPSR CPSR CPSR CPSR CPSR SPSR FIQ SPSR IRQ SPSR SVC SPSR ABT SPSR UND IRQ Supervisor Abort Undefined User/System FIQ 15
Current Program Status Register (CPSR) 31 Flags Status Extension Control 0 N Z C V Q X X J I F T m m m m m Status and Flags Control Mode control Extension byte are 10000 - User N - Negative I - Disable IRQ not used in 10001 - FIQ Z - Zero F - Disable FIQ 10010 - IRQ RaspberryPi. C - Carry T - Thumb state 10011 - Supervisor V - Overflow 10111 - Abort Q - Saturation Flag 11011 - Undefined J - Jazzelle State Bit 11111 - System SPSR (Saved State Program Register) is accessible in privileged modes & has same structure as CPSR . 16
31 24 Flags N Z C V Q X X J N Negative Set if the current operation results in a negative value. Z Zero Set if the current operation results in a zero value. C Carry Set if the current operation results in a zero value. Set if the current operation resulted in a carry which flipped the sign of V Overflow result. Q Saturation Flag Set if the current operation saturated the result register. If processor is in jazzelle mode, it can execute a subset of Java J Jazzelle State Bit bytecode directly. 17
Assembly Instructions used in TOS Instruction Usage add <dest>, <value1>, <value2> ADD adds two values. The value1 comes from a register. The value2 can be either an immediate value or a value from a register, the result is stored to dest register. B (Branch) and BL (Branch and Link) cause a branch to a target address, and provide both conditional and unconditional changes to program flow. BL also stores b{l} <target_address> a return address in the link register, R14. CMP (Compare) compares two values. The first value comes from a register. The cmp <value1>, <value2> second value can be either an immediate value or a value from a register. MOV (Move) writes a value to the destination register. The value can be either an mov <des>, <src> immediate value or a value from a register. POP (Pop Multiple Registers) loads a subset (or possibly all) of the general-purpose pop {r4, r5} registers and the PC. from the stack. PUSH (Push Multiple Registers) stores a subset (or possibly all) of the general- push {r4, r5} purpose registers and the LIB to the stack. 18
Recommend
More recommend
