Assembly Language Programming Introduction to ARM Zbigniew Jurkiewicz, Instytut Informatyki UW December 19, 2017 Zbigniew Jurkiewicz, Instytut Informatyki UW Assembly Language Programming Introduction to ARM
Historia ARM Ltd. company has been created in 1990 as Advanced RISC Machines Ltd., joint venture of Acorn Computers, Apple Computer and VLSI Technology. The assets of company is intellectual property, is is said that it is “ fabless ” (from fabricate ): does not produce chips by itself. The company concentrates on designing the processors from the ARM family. The designs are licenced to partner companies, which produce chips and sell them. Due to this schema the company is able to control the architecture of ARM. Zbigniew Jurkiewicz, Instytut Informatyki UW Assembly Language Programming Introduction to ARM
History First ARM processor was designed in 1983 in English company Acorn, for the processor of the same name. None of the existing at that time 16-bit processors satisfied their requierements, so they designed own customized 32-bit processors. many sources say it was the first commercial RISC. Zbigniew Jurkiewicz, Instytut Informatyki UW Assembly Language Programming Introduction to ARM
History Other companies became interested in this processor. Apple needed a processor for the project PDA (later renamed Newton MessagePad). This caused a split of processor group from Acorn company and creattion of Advanced RISC Machines Ltd. Zbigniew Jurkiewicz, Instytut Informatyki UW Assembly Language Programming Introduction to ARM
ARM Market of (cheap) embedded processors 2 mld of processors in 2005 Cell phones, modems, brake control in cars The whole family of processors — designs customized to various needs. More than 50 supported operating systems. ARM core if often a part of larger circuit, sold by a final producer. Zbigniew Jurkiewicz, Instytut Informatyki UW Assembly Language Programming Introduction to ARM
Architecture Now there exist 8 basic versions of architecture. Each versions is based on the previous one (but note the large change between Classic and Cortex ARM). Architecture version number is completely different from model numbers, for example the models of ARM9 can implement architecture version ARMv4 or ARMv5. Zbigniew Jurkiewicz, Instytut Informatyki UW Assembly Language Programming Introduction to ARM
Classic architecture Mostly 32-bit processor, but Two (basic) sets of instructions: ARM (32 bits) and Thumb (16 bits) Owing to this the memory consumption could be less in necessary Usually no arithmetic division, simulated by code In base versions to floating-point numbers, simulated as above Extensions for processing signals (DSP — Digital Signal Processing ) Efficient handling of exceptions. Zbigniew Jurkiewicz, Instytut Informatyki UW Assembly Language Programming Introduction to ARM
RISC RISC architecture ( Reduced Instruction Set Computer ) Simple instructions of the same size, less classes of instructions The same execution time: one processor cycle = one instruction Pipeline processing, many registers All registers are universal, load-store architecture Complexity in compiler, not in processor Direct realization without microprogramming Complicated operations (e.g. division) often implemented in software Zbigniew Jurkiewicz, Instytut Informatyki UW Assembly Language Programming Introduction to ARM
ARM architecture Based on RISC concepts, but slightly different priorities Small power consumption, because usually supplied from battery. Dense instruction packing, because of limited memory. Small space taken by processor in single-chip circuits gives more place for other elements. Restrictions on costs. Zbigniew Jurkiewicz, Instytut Informatyki UW Assembly Language Programming Introduction to ARM
ARM architecture Differences as compared to “pure” RISC Variable execution time for single instructions, e.g load-store-multiple , which loads a sequence of memory cells to consecutive registers. Barrel-shifter for one of input registers — additional increase in instruction execution time. Alternative 16-bit instruction set Thumb Conditionally executed instructions Extended instructions for DSP (e.g. 16x16 bits multiplication and saturation) Zbigniew Jurkiewicz, Instytut Informatyki UW Assembly Language Programming Introduction to ARM
ARM architecture Buses with AMBA protocol ( Advanced Microcontroller Bus Architecture ) All devices are memory-mapped access to device registers same as to memory cells additional instructions unnecessary Zbigniew Jurkiewicz, Instytut Informatyki UW Assembly Language Programming Introduction to ARM
ISA 32-bit registers Computational instructions: 2 source registers + destination register 7 working modes, normal one is called user . Zbigniew Jurkiewicz, Instytut Informatyki UW Assembly Language Programming Introduction to ARM
Registers For modes user and system 16 active universal registers r0-r15 and processor state register cpsr. Some register have special purpose and additional names r13 (sp) — stack pointer r14 (lr) — link register : to save return address when calling procedures r15 (pc) — program counter There are instructions, which treat registers r14 and r15 in special ways. Zbigniew Jurkiewicz, Instytut Informatyki UW Assembly Language Programming Introduction to ARM
Processor state register Actually there are two processor state registers cpsr — current program status register spsr — saved program status register : accessible only in priviledged modes. Fields: 4 flags for operation results: N, Z, C, V Additional flags in some models J (Jazelle) to execute 8-bit Java instruction set Q for saturation in DSP extensions Processor work mode Two interrupt masks I and F (ordinary nad fast interrupts) T: selection of Thumb instruction set Zbigniew Jurkiewicz, Instytut Informatyki UW Assembly Language Programming Introduction to ARM
Processor work modes user (usr): unpriviledged system (sys): like user , but arbitrary changing of status register is allowed abort (abt): after incorrect reference to memory undefined (und): after encountering undefined or unimplemented instructions fast interrupt request (fiq) and interrupt request (irq): for two interrupt levels supervisor (svc): initial state, used also for operating system kernel and after reset. Additional private register banks for priviledged modes, they replace registers r13 nad r14; for fast interrupts also r8–r12. They add spsr register. Zbigniew Jurkiewicz, Instytut Informatyki UW Assembly Language Programming Introduction to ARM
Instructions We will start with the simplest instruction. MOV r0,r1 MOV r4,#10 It stores in a register the contents of other register or constant. Sufix S causes setting of flags, ever in MOV instruction MOVS r0,r1 Zbigniew Jurkiewicz, Instytut Informatyki UW Assembly Language Programming Introduction to ARM
Instructions Second (or the only one) argument of an instruction may be additionally rotated or shifted, for example the instruction MOV r0,r1,LSL #2 corresponds to shifting the contents of r1 two bitss to the left with storing the result in r0. Other example with the computed shift: MOV r0,r1,ASR r3 Zbigniew Jurkiewicz, Instytut Informatyki UW Assembly Language Programming Introduction to ARM
Computed jump If the destination register of an instruction (not only for MOV!) is pc register, the it works as a jump to the computed address, for example MOV pc,r1 If r1 contains the address of jump table, then to select one of them ADD pc,r1,r2 LSL #2 In such situation flags may be set in priviledged modes. Zbigniew Jurkiewicz, Instytut Informatyki UW Assembly Language Programming Introduction to ARM
Conditional execution Most instructions can have special suffix, restricting additionally (by state flags) when they will execute, e.g. the instruction MOVEQS r0,r1,ASR r3 will be executed only when the zero flag is set (and it will itself change flags). Some available suffixes: AL ( always , default), EQ, NE, GT, LE, LT, GE, MI, PL. Zbigniew Jurkiewicz, Instytut Informatyki UW Assembly Language Programming Introduction to ARM
Conditional execution Example: computing GCD of two integers define function gcd (a :: <integer>, b :: <integer>) => (r :: <integer>) while (a ~= b) if (a > b) a := a - b; else b := b - a; end if; end while; a end function; Zbigniew Jurkiewicz, Instytut Informatyki UW Assembly Language Programming Introduction to ARM
Conditional execution For assembler version we assume, that arguments are in registers r0 and r1, and the result must be in r0. without conditional execution gcd CMP r0,r1 BEQ finish BLT less SUB r0,r0,r1 B gcd less SUB r1,r1,r0 B gcd finish BX lr ;??? Zbigniew Jurkiewicz, Instytut Informatyki UW Assembly Language Programming Introduction to ARM
Conditional execution with conditional execution gcd CMP r0,r1 SUBGT r0,r0,r1 SUBLT r1,r1,r0 BNE gcd BX lr ;??? Zbigniew Jurkiewicz, Instytut Informatyki UW Assembly Language Programming Introduction to ARM
Arithmetic instructions Addition and subtraction for integers with and without sign, as usual the first argument must be a register. ;multiplication by 3 ADD r0,r1,r1,LSL #1 Reversed subtraction ;negacja RSB r0,r1,#0 RSC r4,r1,r2,LSL #1 Zbigniew Jurkiewicz, Instytut Informatyki UW Assembly Language Programming Introduction to ARM
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