Tightening worst-case timing analysis of Tilera-like NoC - PowerPoint PPT Presentation

Tightening worst-case timing analysis of Tilera-like NoC architecture Hamdi Ayed, Jérôme Ermont, Jean-luc Scharbarg, Christian Fraboul University of Toulouse 18th Euromicro Conference on Real-Time Systems ECRTS 2016 WiP session

Network-on-Chip (NoC) N 2 N 3 N 1 Processing Element N i R 1 R 2 R 3 /Memory Controller /Off-chip interface N 4 N 5 N 6 R i Router R 6 R 4 R 5 N 7 N 8 N 9 R 9 R 7 R 8 Tightening worst-case timing analysis of Tilera-like NoC architecture 1

Network-on-Chip (NoC) ● NoC for real-time applications → Bounded network latency → Worst-case traversal time (WCTT) analysis Tightening worst-case timing analysis of Tilera-like NoC architecture 1

Network-on-Chip (NoC) ● NoC for real-time applications → Bounded network latency → Worst-case traversal time (WCTT) analysis ● Timing analysis techniques – Network calculus (NC) – Recursive calculus (RC) Tightening worst-case timing analysis of Tilera-like NoC architecture 1

Network-on-Chip (NoC) ● NoC for real-time applications → Bounded network latency → Worst-case traversal time (WCTT) analysis ● Timing analysis techniques – Network calculus (NC) – Recursive calculus (RC) ● Our study – Tilera TILE64-like NoC – Improve WCTT bounds of Recursive Calculus analysis Tightening worst-case timing analysis of Tilera-like NoC architecture 1

Existing recursive timing analysis N 2 N 3 ● Wormhole routing f 2 N 1 f 3 f 1 ● Round robin arbitration R 1 R 2 R 3 ● Flow level analysis N 4 f 4 R 4 – Ignores available buffer capacity N 5 – Maximal flow rate R 5 assumption N 6 f 5 R 6 N 7 R 7 Tightening worst-case timing analysis of Tilera-like NoC architecture 2

Existing recursive timing analysis N 2 N 3 ● Wormhole routing f 2 N 1 f 1 ● Round robin arbitration R 1 R 2 R 3 ● Flow level analysis N 4 R 4 – Ignores available buffer capacity N 5 – Maximal flow rate R 5 assumption N 6 → {f 2 , f 1 } R 6 N 7 R 7 Tightening worst-case timing analysis of Tilera-like NoC architecture 2

Existing recursive timing analysis N 2 N 3 ● Wormhole routing f 2 N 1 f 3 f 1 ● Round robin arbitration R 1 R 2 R 3 ● Flow level analysis N 4 R 4 – Ignores available buffer capacity N 5 – Maximal flow rate R 5 assumption N 6 → {f 3 , f 2 , f 1 } R 6 N 7 R 7 Tightening worst-case timing analysis of Tilera-like NoC architecture 2

Existing recursive timing analysis N 2 N 3 ● Wormhole routing f 2 N 1 f 3 f 1 ● Round robin arbitration R 1 R 2 R 3 ● Flow level analysis N 4 f 4 R 4 – Ignores available buffer capacity N 5 – Maximal flow rate R 5 assumption N 6 → {f 4 , f 3 , f 2 , f 1 } R 6 N 7 R 7 Tightening worst-case timing analysis of Tilera-like NoC architecture 2

Existing recursive timing analysis N 2 N 3 ● Wormhole routing f 2 N 1 f 3 f 1 ● Round robin arbitration R 1 R 2 R 3 ● Flow level analysis N 4 R 4 – Ignores available buffer capacity N 5 – Maximal flow rate R 5 assumption N 6 f 5 → {f 5 , f 4 , f 3 , f 2 , f 1 } R 6 N 7 R 7 Tightening worst-case timing analysis of Tilera-like NoC architecture 2

Existing recursive timing analysis N 2 N 3 ● Wormhole routing f 2 N 1 f 3 f 1 ● Round robin arbitration R 1 R 2 R 3 ● Flow level analysis N 4 R 4 – Ignores available buffer capacity N 5 – Maximal flow rate R 5 assumption N 6 → {f 5 , f 4 , f 3 , f 2 , f 1 } R 6 N 7 R 7 Tightening worst-case timing analysis of Tilera-like NoC architecture 2

Existing recursive timing analysis N 2 N 3 ● Wormhole routing f 2 N 1 f 1 ● Round robin arbitration R 1 R 2 R 3 ● Flow level analysis N 4 R 4 – Ignores available buffer capacity N 5 – Maximal flow rate R 5 assumption N 6 → {f 5 , f 4 , f 3 , f 2 , f 1 } R 6 N 7 R 7 Tightening worst-case timing analysis of Tilera-like NoC architecture 2

Existing recursive timing analysis N 2 N 3 ● Wormhole routing f 2 N 1 f 1 ● Round robin arbitration R 1 R 2 R 3 ● Flow level analysis N 4 R 4 – Ignores available buffer capacity N 5 – Maximal flow rate R 5 assumption N 6 → {f 5 , f 4 , f 3 , f 2 , f 1 } R 6 N 7 R 7 Tightening worst-case timing analysis of Tilera-like NoC architecture 2

Existing recursive timing analysis N 2 N 3 ● Wormhole routing N 1 f 1 ● Round robin arbitration R 1 R 2 R 3 ● Flow level analysis N 4 R 4 – Ignores available buffer capacity N 5 – Maximal flow rate R 5 assumption N 6 → {f 5 , f 4 , f 3 , f 2 , f 1 } R 6 N 7 R 7 Tightening worst-case timing analysis of Tilera-like NoC architecture 2

Existing recursive timing analysis N 2 N 3 ● Wormhole routing N 1 f 3 f 1 ● Round robin arbitration R 1 R 2 R 3 ● Flow level analysis N 4 R 4 – Ignores available buffer capacity N 5 – Maximal flow rate R 5 assumption N 6 → {f 5 , f 4 , f 3 , f 2 , f 3 , f 1 } R 6 N 7 R 7 Tightening worst-case timing analysis of Tilera-like NoC architecture 2

Existing recursive timing analysis N 2 N 3 ● Wormhole routing N 1 f 3 f 1 ● Round robin arbitration R 1 R 2 R 3 ● Flow level analysis N 4 f 4 R 4 – Ignores available buffer capacity N 5 – Maximal flow rate R 5 assumption N 6 f 5 → {f 5 , f 4 , f 3 , f 2 , f 5 , f 4 , f 3 , f 1 } R 6 N 7 R 7 Tightening worst-case timing analysis of Tilera-like NoC architecture 2

Existing recursive timing analysis N 2 N 3 ● Wormhole routing N 1 f 1 ● Round robin arbitration R 1 R 2 R 3 ● Flow level analysis N 4 R 4 – Ignores available buffer capacity N 5 – Maximal flow rate R 5 assumption N 6 → {f 5 , f 4 , f 3 , f 2 , f 5 , f 4 , f 3 , f 1 } R 6 N 7 R 7 Tightening worst-case timing analysis of Tilera-like NoC architecture 2

Existing recursive timing analysis N 2 N 3 ● Wormhole routing N 1 f 1 ● Round robin arbitration R 1 R 2 R 3 ● Flow level analysis N 4 R 4 – Ignores available buffer capacity N 5 – Maximal flow rate R 5 assumption N 6 → {f 5 , f 4 , f 3 , f 2 , f 5 , f 4 , f 3 , f 1 } R 6 N 7 - Packet size = 4 flits R 7 - Transmission rate = 1 flit/cycle → WCTT(f 1 ) = 55 cycles Tightening worst-case timing analysis of Tilera-like NoC architecture 2

Enhanced approach N 2 N 3 ● Buffer effect f 2 N 1 f 3 f 1 Buffer size = 3 flits – R 1 R 2 R 3 → f 5 has no impact on f 1 N 4 f 4 ● Minimim inter-release time R 4 → bounded number of packets N 5 released during [a,a+t] R 5 N 6 f 5 j n j n+1 N j R 6 T N 7 R l j n j n+1 R 7 T-J Rl Nb ( f j , R l ,t )= ⌈ R l ⌉ t → 0 ( f ))= 1 Nb ( f 3 ,R 2 ,WCTT T j − J j Tightening worst-case timing analysis of Tilera-like NoC architecture 3

Enhanced approach N 2 N 3 ● Buffer effect f 2 N 1 f 3 f 1 {f 5 , f 4 , f 3 , f 2 , f 5 , f 4 , f 3 , f 1 } R 1 R 2 R 3 ● Minimim inter-release time N 4 f 4 R 4 {f 5 , f 4 , f 3 , f 2 , f 5 , f 4 , f 3 , f 1 } N 5 or R 5 {f 5 , f 4 , f 3 , f 2 , f 5 , f 4 , f 3 , f 1 } N 6 f 5 or R 6 {f 5 , f 4 , f 3 , f 2 , f 5 , f 4 , f 3 , f 1 } N 7 or … R 7 Tightening worst-case timing analysis of Tilera-like NoC architecture 3

Enhanced approach N 2 N 3 ● Combined effect f 2 N 1 f 3 f 1 {f 5 , f 4 , f 3 , f 2 , f 5 , f 4 , f 3 , f 1 } R 1 R 2 R 3 N 4 f 4 or R 4 {f 5 , f 4 , f 3 , f 2 , f 5 , f 4 , f 3 , f 1 } N 5 1 ( f 1 )= 24 cycles WCTT → R 5 N 6 f 5 ● Iteration to convergence R 6 n + 1 ( f 1 )= WCTT n ( f 1 ) Stop when WCTT – N 7 R 7 Tightening worst-case timing analysis of Tilera-like NoC architecture 3

Preliminary results - Real-time application flow Period Packet size (cycles) (flits) f i 500 10 flow Initial RC Buffer Period Combined bounds effect effect effect (cycles) (cycles) (cycles) (cycles) f1 304 251 121 111 f2 304 264 121 98 f3 143 112 86 78 f4 143 127 86 79 f5 44 40 27 25 f6 24 24 23 22 f7 27 25 25 23 Up to 65 % WCTT bound reduction f8 24 24 23 22 f9 167 145 89 82 f10 50 44 30 27 Tightening worst-case timing analysis of Tilera-like NoC architecture 4