The CMS Inner Tracker Upgrade for the HL-LHC Malte Backhaus for the - PowerPoint PPT Presentation

The CMS Inner Tracker Upgrade for the HL-LHC Malte Backhaus for the CMS Collaboration Malte Backhaus | PIXEL2018 | | 10/12/2018 | | 1

Motivation and requirements Experimental conditions at HL-LHC Luminosity increase by factor 7.5 to ~10 35 cm -2 s -1   200 pile-up vertices  10.000 particle tracks per event  25 ns bunch-crossing separation Collect up to 4000 fb -1 of data   ~10 years of operation Innermost layer: 2.3x10 16 n eq /cm 2  3.8 T magnetic field Outer & Service cylinder: 10 15 n eq /cm 2 Requirements for the CMS Tracker in Phase 2  Provide trigger information using transverse momentum of tracks  p T -modules in Outer Tracker  latency increase to 12.5 μ s (currently 3.75 μ s)  Trigger rate increase to 750 kHz Occupancy of up to 3.5 GHz/cm 2 in pixel layer one   Radiation levels up to fluence of 2.3 x 10 16 1 MeV n eq cm -2  Innermost layer: 1.2 Grad  Total ionizing dose of 1.2 Grad Outer & Service cylinder: 100Mrad Malte Backhaus | PIXEL2018 | 10/12/2018 | 2

CMS Phase 2 Tracker Outer Tracker: Strip-strip p t -modules Strip-pixel p t -modules Inner Tracker: 2x2 pixel modules 1x2 pixel modules EDR TDR EDR Pixel Phase 2 Pixel Phase 1 Installation Installation Malte Backhaus | PIXEL2018 | 10/12/2018 | 3

IT overview Dimensions ~4.9 m2 of pixel surface, 2 billion channels Simple mechanics no turbines-tilted modules Simple installation/removal for potential replacement/repair of parts IT volume increase at z = 1600mm installation from both sides in 8 parts Tracker Extension PiXel Tracker Barrel PiXel 4 disks 4 layers Tracker Forward PiXel 8 disks Malte Backhaus | PIXEL2018 | 10/12/2018 | 4

IT layout 2x2 and 1x2 modules TEPX TFPX TBPX New proposal TEPX: TBPX: TFPX: • 4 disks/end • 4 layers • 8 disks per side • 5 rings/disk • 4/5 modules per ladder • 4 rings per disk Malte Backhaus | PIXEL2018 | 10/12/2018 | 5

Major challenges (focussed on in this talk) Sensor  radiation tolerance efficiency, power consumption  track density hit occupancy (cluster size in magnetic field) Readout chip  radiation tolerance hit occupancy, trigger latency  hit occupancy, trigger latency power consumption Pixel modules  low mass power consumption, data rate  removable connection to chains, thermal management Detector system  power consumption low mass services Mechanics  lightweight and removable mechanics high thermal load Malte Backhaus | PIXEL2018 | 10/12/2018 | 6

Sensor design and testing n-in-p sensors with: 25x100 μ m 2 (baseline) 50x50 μ m 2 Radiation tolerance  thin sensors: 100-150 µm thickness: 1. expected signal / threshold > 3 at Φ eq ≈ 8x10 15 cm -2 Track density  reduce pixel size by factor of six: 2. 25x100 or 50x50 µm 2 under study High efficiency  pixel cell design: 3. Isolation, biasing scheme, layout details 3D sensors:  See poster by M. Meschini CMS sensors bump-bonded to RD53A chips allows to test to required radiation levels: Light carrier board for irradiation campaigns ( 88 sensors ) and tests beams in 2018-2019 Simulation J. Schwandt Expected threshold CMS ROC Malte Backhaus | PIXEL2018 | 10/12/2018 | 7

Thin n-in-p test-beam • RD53A Single chip assembly, in-pixel efficiency of four pixel cell shown • Beam at vertical incidence (as in TFPX and TEPX) Higher efficiency with bias dot floating Malte Backhaus | PIXEL2018 | 10/12/2018 | 8

Thin n-in-p test-beam • RD53A Single chip assembly, in-pixel cluster size map of four pixel cell shown • Beam at vertical incidence (as in TFPX and TEPX) Higher (better) charge sharing between pixels with bias dot floating Malte Backhaus | PIXEL2018 | 10/12/2018 | 9

RD53 readout chip - common design with ATLAS RD53A chip ( ½ size of final chip) Design features: 50 x 50 µm 2 pixels • • 3 Analog Front-Ends • 2 digital architectures • Shunt-LDO for serial powering • 4 x 1.28 Gbps output links • 1 x 160 Mbps control link Technology and design concept: • 65nm feature size • Analog islands (manual layout) in a Digital Sea (synthesized)  Intense modelling and verification prior to submission RD53A functional floorplan Active test program: • Chip is fully functional • Meeting 500 Mrad tolerance specification  Could reach 1 Grad (controlled conditions)? • All Analog Front-Ends show good performance with radiation • Low Threshold < 1000e - Working intensively on RD53B design CMS final chip submission: End of 2019 Malte Backhaus | PIXEL2018 | 10/12/2018 | 10

RD53 readout chip μ = 64 e σ = 4 e Malte Backhaus | PIXEL2018 | 10/12/2018 | 11

RD53 readout chip RD53A Measurement vs. simulation RD53A chip rate capability: • Measure hit processing efficiency as a function of Xray flux • Buffer architecture optimized for clusters, not for isolated Xray hits • 12.5 μ s latency: • sensitive to digital buffer losses • 3.75 μ s latency: • sensitive to dead time only • Expected to meet the design specs of 99% efficiency at 3.0 GHz/cm 2 with clustered hits [TDR]  will measure in high rate particle beam More details: D. Ruini , Serial Powering for the Phase 2 upgrade of the CMS pixel detector Xray Malte Backhaus | PIXEL2018 | 10/12/2018 | 12

Pixel Modules Concept:  Simple design, ROC only active electronics on module Constraints from geometry:  Both faces of TBPX ladders loaded with modules  no service routing on back-side  supply current (and return) directly from module to module  TFPX and TEPX :  service routing on “inactive” dee surface  current entries and exits module at the same side  Section dedicated module layout per detector section 2x2 1x2 Malte Backhaus | PIXEL2018 | 10/12/2018 | 13

Prototype modules using RD53A Noise distribution on Module μ = 67 e σ = 5 e Noise with similar settings as on PCB. Charge and reference current not calibrated Top layer, P = 200mW  TBPX type HDI with aggressive design produced:  Thin copper layers  Small pitch  RD53A modules build, first experience:  Design tested to 1kV sensor bias voltage  Current distribution and communication working  ROC performance as on PCB Malte Backhaus | PIXEL2018 | 10/12/2018 | 14

Serial Powering   Challenge Solution Consequence   High occupancy small/many/fast pixels high supply current   Long latency time Large buffers, small feature size high supply current Future CMS pixel detector requires ~50 kW / ~30kA on-detector power / supply current.  Power-loss in cables not tolerable. A reduction of factor 8-10 required. Serial powering is the only viable solution for powering Phase 2 pixels… ... never attempted before in a HEP experiment! R cable very large due to ~100 m long cables Malte Backhaus | PIXEL2018 | 10/12/2018 | 15

Serial Powering Across-module serial powering: Current “re -used ” among n loads in series  Reduces current in cable resistances by n  System power efficiency increases with n 2 Requires: • Constant total current constant  independent of actual load in chips • Defined current sharing among parallel chips  ohmic behavior of chips Consequence: • Additional logic on chip  ShuntLDO • Enough current injected to satisfy highest loads  any extra current (not used by load) gets burnt by shunts • Not sensitive to voltage drops  low cable cross section  low mass • Modules grounds / sensors bias differ inside a chain Malte Backhaus | PIXEL2018 | 10/12/2018 | 16

Serial Powering Pixel to pixel noise difference VI-behavior of the first two RD53A between parallel and serial modules powering mode  Very active SP community across ATLAS and CMS  Quickly gaining experience and confidence  Still many developments ahead Detailed talks: S. Kuehn: Results of larger structures prototyping for the Phase-II upgrade of the pixel detector of the ATLAS experiment D. Ruini: Serial Powering for the Phase 2 upgrade of the CMS pixel detector Serial powering concept very reliable and robust Malte Backhaus | PIXEL2018 | 10/12/2018 | 17

TBPX support structure chip 1 fails chip 2 fails  Thermal modelling T max – T CO2 [C]  including all materials and interfaces  Improvements under study  Module power consumption including Layer 1  Readout chips in normal operations and in failure modes  Sensor power consumption as function of fluence and temperature T max – T CO2 [C]  HDI Layer 2 T CO2 [C] T max – T CO2 [C] Layer 3/4 TBPX L1 cooling pipes Example of TBPX L3 driven below the chip hotspots module thermal modelling T CO2 [C] Malte Backhaus | PIXEL2018 | 10/12/2018 | 18

TFPX support structure A ½ disk is composed of Modules two Dees: - Odd dee: ring 1+ring 3 Carbon fibre skin - Even dee: ring 2+ring 4 Carbon foam Modules of arranged on both sides of a dee- CO 2 cooling loop "sandwich ” structure Modules Malte Backhaus | PIXEL2018 | 10/12/2018 | 19