Silicon strip staves and petals for the ATLAS Upgrade tracker of the HL-LHC Sergio Díez Cornell, Berkeley Lab (USA), On behalf of the ATLAS Upgrade strip tracker Collaboration HSTD-8, Taipei, Taiwan, Dec 5th-8th, 2011
Motivation: ATLAS Phase II Upgrade (HL-LHC) Numerous challenges for silicon sensors on ATLAS Phase-II Upgrade Higher granularity to keep same low occupancy Higher radiation tolerance to deal with increased radiation environment Novel powering solutions to power efficiently x7.5 more channels Maintain low cable count to keep detector performance Reduce cost per sensor to cover larger area (~ 200 m 2 ) Replacement of ATLAS Inner detector by an all-silicon tracker: Strips tracker : Si tracker (Utopia Layout) 3 layers of short strips (2.5 cm) 300 cm staves 2 layers of long strips (9.6 cm) staves 75 cm 10 disks of endcap petals 06/12/2011 S. Díez Cornell, HSTD-8, Taipei (Taiwan) 2
Stave concept layout and current prototypes Barrel strip stave (short strip version): 1.2 m 12 cm Designed to minimize material Stave cross-section: • Shortened cooling paths Readout ICs Kapton flex hybrid Cu bus • Module glued to stave core with embedded pipes tape • No substrate or connectors, hybrids glued to sensors Designed for large scale assembly Ti coolant tube • Simplified build procedure Carbon fiber facing All components testable independently Aimed to be low-cost Si Strip sensor Carbon honeycomb High T conductivity foam • Minimize specialist components Short strip module: “Stavelets”: • Stave prototype with 4 modules per side • 1 n-in-p strip sensor with • Single-sided stavelets (serial and DC-DC powered) 4 x2.5cm strips already built and under test at RAL [1] • 2 hybrids, each with 10 ABCN130 (256 ch) + 1 HCC/hybrid • Binary readout • Current prototypes: ABCN250 (128 ch/chip) + BCCs 06/12/2011 S. Díez Cornell, HSTD-8, Taipei (Taiwan) 3
Stave/petal powering LV: Two powering distributions under study for n hybrids, each with current I 1 2 3 4 5 6 n-1 n Serial powering • Total current = I Constant • Different GND levels per hybrid …… current • AC coupling of data lines source • Bypass protection required 1 2 3 4 5 6 n-1 n DC-DC powering • Total current = n·(I/r * ) • Switching system …… Constant • Can be noisy voltage • + High mass source - *r = voltage conversion ratio HV: Parallel power limited by cable reuse and/or material limitations HV rad-hard switching for multiplexing under study recently (early stage) [2] Current module and stave prototypes have proven to be a powerful test bench for the different powering options considered 06/12/2011 S. Díez Cornell, HSTD-8, Taipei (Taiwan) 4
Other components of the stavelet prototypes Basic Control Chip (BCC) boards for data I/O (1 per hybrid) AC coupled multi-drop system LVDS reception Generates 80 MHz DCLK and handles 160Mb/s multiplexed data from each hybrid Serial powering: Power Protection Board (PPB) [3] 39x6 mm 2 Fast response and slow-control bypass of modules within an SP chain Allows alternate SP shunt circuits Excellent performances demonstrated on SP stavelet All hybrids on Slow control disables odd hybrids SPP ASIC submitted Aug 2011 V = 22.7 V, I = 5.09 A V = 12.7 V, I = 5.09 A DC-DC powering: buck DC-DC converter AMIS4 Custom low-mass inductor and shield [4] AMIS 4 ASIC: • Over current, over temperature, input under- voltage, and soft start state machine for reliable start-up procedure [5] 13x28 mm 2 New prototype circuits underway 06/12/2011 S. Díez Cornell, HSTD-8, Taipei (Taiwan) 5
Stave modules production and tools Scalability for large scale production even at prototyping stage Panelization of laminated hybrids • Designed for machine placement of passives and solder reflow • Tools developed for controlled gluing and wire bonding of ABCNs • Conservative design rules for high yield and volume, and low cost • Final hybrids testable on panels, ready for module assembly Diverse tools developed for uniform gluing of hybrids to sensors • Numerous options investigated: glue spread on sensor or hybrid backplane, different glue stencils,… • Optimized glue thickness for best module performances: ~ 120 μ m Automated wire bonding of ASICs to sensor and hybrids to test frames Fully testable modules, ready for stave assembly 06/12/2011 S. Díez Cornell, HSTD-8, Taipei (Taiwan) 6
Stave module testing PCB test frames: cheap and flexible test benches for testing Different power configurations, G&S, added circuitry … DAQ system for stave modules and stavelets: HSIO Generic DAQ board (ATCA form factor) with single (large) Virtex-4 FPGA for data processing & connection to controller PC Interface board: connectors & buffers for connectivity to FEE Currently supports up to 64 streams (>64 streams with larger FX100 FPGA in future) Upgraded sctdaq software Allows standard 3ptGain, Response Curve, Noise Occupancy, DT Liverpool Noise,… on ABCN -250 modules Expected noise performances for parallel, serial, and DC-DC powered modules Similar ENC noise performances obtained at the different sites Berkeley, serial Freiburg, serial 06/12/2011 S. Díez Cornell, HSTD-8, Taipei (Taiwan) 7
Stave module construction and test Numerous institutes involved in the construction and test of stave modules and stavelets [6] Up to 31 modules built so far (Nov 2011) 06/12/2011 S. Díez Cornell, HSTD-8, Taipei (Taiwan) 8
Proton irradiations of stave modules Irradiated at CERN-PS 24 GeV proton beam scanned over inclined modules Module biased, powered, and clocked during irradiation Up to 2x10 15 cm -2 reached Sensor and module behave as expected • Noise increase consistent with shot noise expectations Slide borrowed from T. Affolder, TIPP2011, June 2011 06/12/2011 S. Díez Cornell, HSTD-8, Taipei (Taiwan) 9
Stavelets Stave prototypes with 4 modules per Power and PPBs side SP stavelet Sensors directly glued to bus tape with EOS “soft” glue for easy module replacement board or removal Key test bed for electrical testing Powering, protection, G&S, … Single-sided serial and DC-DC powered stavelets built and tested so far Custom Cu bus tape BCCs SP stavelet tested with custom constant Power and Buck DC-DC converters current source (0-6A, OVP), excellent performances [7] DC-DC stavelet EOS board Custom Cu bus tape BCCs 06/12/2011 S. Díez Cornell, HSTD-8, Taipei (Taiwan) 10
Stavelet bus tape layout SP shield Layer (Al) SP Trace Layer (Cu) HV SP Current Return LVDS Clock/Command/Data & NTC 100 μ m track/gap over 40cm (1.2m) 11 For DC-DC, the power section of the SP tape is cut off and replaced by a custom section Slide borrowed from P. Phillips, 06/12/2011 S. Díez Cornell, HSTD-8, Taipei (Taiwan) 11 TWEPP2011,Sept2011
Electrical tests on stavelets ENC noise close to noise on individual modules for both stavelets Approximately ~ 20e higher in both cases SP stavelet: PPB and bypassing hybrids does not affect noise performances Double Trigger Noise clean at 1 and 0.75fC with appropriate current routing Slightly better DT Noise performances at 0.5fC for DC-DC stavelet Still work in progress [1] Serially powered stavelet H0 H1 H2 H3 H4 H5 H6 H7 Column 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ENC 661 623 628 675 650 636 697 760 687 646 640 666 680 661 624 656 DTN @1.0fC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTN @0.75fC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTN @0.5fC 130 40 1 58 3 1 255 1181 32 4 56 102 50 26 50 237 DC-DC powered stavelet H0 H1 H2 H3 H4 H5 H6 H7 Column 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 dENC 8 1 27 26 11 2 17 26 -10 -9 28 31 -26 -23 -2 -2 DTN @1.0fC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTN @0.75fC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTN @0.5fC 0 1 6 36 18 5 12 38 12 2 4 9 0 0 0 4 06/12/2011 S. Díez Cornell, HSTD-8, Taipei (Taiwan) 12
Stave material estimates Stave material estimates for 130 nm stave [8, 9] : Based on as-built stavelets Adhesives %X0 3% Stave core 0.55% Stave core 28% Bus tapes 0.30% Modules Modules 1.07% Stave core 54% Tapes Bus tapes Module to stave adhesives 0.06% 15% Modules TOTAL 1.98% Module to stave adhesives Titanium cooling tube: 2.2mm OD x 0.14mm wall Tapes contribution could be significantly reduced (~50%) by removing Al screen + one glue layer: under investigation Sensor dominates module material (~ 63%) Power components will add 0.03 - 0.15 %X0, depending on power scheme (first approximation: changes in bus tape not considered) 06/12/2011 S. Díez Cornell, HSTD-8, Taipei (Taiwan) 13
Endcap petals: Petalet program The endcap petal follows closely the barrel stave design First petal cores already been produced First endcap hybrids (ABCN-250 ASICs) produced and tested Petalet prototype underway Combines innermost radius sensors and region where petal splits in 2 sensor columns [10] Endcap hybrid “Petalet” 06/12/2011 S. Díez Cornell, HSTD-8, Taipei (Taiwan) 14
Recommend
More recommend