TEE Boot Procedure with Crypto-accelerators in RISC-V Processors Authors: Ckristian Duran, Trong-Thuc Hoang, Akira Tsukamoto, Kuniyasu Suzaki, and Cong-Kha Pham
Outline ● Motivation ● Hardware Structure for Trusted Execution Environments ● Boot Procedure with Crypto-accelerators ● Implementation Results ● Conclusions 2
Outline ● Motivation ● Hardware Structure for Trusted Execution Environments ● Boot Procedure with Crypto-accelerators ● Implementation Results ● Conclusions 3
RISC-V Processor Privilege Modes 0x00000000 Debug Reset Vector ROM Devices RAM 0xFFFFFFFF RISC-V Processor M-mode 4
RISC-V Processor Privilege Modes 0x00000000 Debug ROM - Boot Procedure Reset Vector ROM Copy Store Jump to BOOTLDR BOOTLDR BOOTLDR from SD in RAM in RAM Devices SD SD commands Card through a SPI Device RAM 0xFFFFFFFF RISC-V Processor M-mode 5
RISC-V Processor Privilege Modes 0x00000000 Debug ROM - Boot Procedure Reset Vector ROM Copy Store Jump to BOOTLDR BOOTLDR BOOTLDR from SD in RAM in RAM Devices BOOTLDR RAM 0xFFFFFFFF RISC-V Processor M-mode 6
RISC-V Processor Privilege Modes 0x00000000 Debug ROM - Boot Procedure ROM Copy Store Jump to BOOTLDR BOOTLDR BOOTLDR from SD in RAM in RAM Devices Execution BOOTLDR RAM 0xFFFFFFFF RISC-V Processor M-mode 7
RISC-V Processor Privilege Modes 0x00000000 0x00000000 Debug Debug ROM Devices Devices Execution BOOTLDR The bootloader extracts Linux and RAM executes it in Execution Linux Supervisor-Mode RAM 0xFFFFFFFF 0xFFFFFFFF RISC-V Processor RISC-V Processor M-mode S-mode 8
RISC-V Processor Privilege Modes 0x00000000 0x00000000 0x00000000 Debug Debug ROM PID 1 Execution App 1 Memory Devices Devices App 2 PID 2 Memory Execution Execution BOOTLDR RAM Execution Linux RAM 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF RISC-V Processor RISC-V Processor RISC-V Processor M-mode S-mode U-mode 9
Non-Protected Applications 0x00000000 Malicious applications can access and execute code arbitrarily. Some attacks PID 1 are: Execution App 1 Memory ● Cache manipulation App 2 ● Privilege mode escalation Memory ● Controlled power glitches PID 2 Malicious Execution App 0xFFFFFFFF RISC-V Processor U-mode 10
Making a Secure Environment 0x00000000 0x00000000 Debug PID 1 Execution App 1 Memory Devices Sign App 2 PID 2 Memory Execution Sign Linux only executes the application if the Execution signature is Linux authenticated. RAM 0xFFFFFFFF 0xFFFFFFFF RISC-V Processor RISC-V Processor S-mode U-mode 11
Making a Secure Environment 0x00000000 0x00000000 Debug PID 1 Once the signature Execution App 1 verification is performed, Memory Devices the attack can rewrite the Sign instructions of any application to execute App 2 unsigned code . Memory Sign PID 2 Unsigned Execution Linux Execution Code RAM 0xFFFFFFFF 0xFFFFFFFF RISC-V Processor RISC-V Processor S-mode U-mode 12
Making the Trusted Execution Environment 0x00000000 0x00000000 0x00000000 Debug Debug ROM PID 1 Execution App 1 Interface Devices Devices Sign Signature and Execution are App 1 performed in the Execution BOOTLDR highest privileged mode RAM Execution Linux RAM 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF RISC-V Processor RISC-V Processor RISC-V Processor M-mode S-mode U-mode 13
RISC-V Lack of Crypto-Hardware Signature Procedure Elliptic App 1 Generate Hashing Curve 16KB Memory Keypair Sign / Ver 164ms at 100MHz clock 14
RISC-V Lack of Crypto-Hardware Signature Procedure Elliptic App 1 Generate Hashing Curve 16KB Memory Keypair Sign / Ver 164ms at 100MHz clock Signature Procedure Elliptic BOOTLDR Generate 2MB Hashing Curve + Linux Keypair Sign / Ver 18.5s at 100MHz clock 15
Outline ● Motivation ● Hardware Structure for Trusted Execution Environment ● Boot Procedure with Crypto-accelerators ● Implementation Results ● Conclusions 16
SoC Architecture ROCKET COREPLEX ROCKET RISC-V CORE 1 ROCKET RISC-V CORE 2 I$ D$ I$ D$ TILELINK SYSTEM BUS (SBUS) MBUS TILELINK PERIPHERAL BUS (PBUS) TL to AXI4 SPI (as SPI (as DDR SHA-3 UART GPIO ROM) MMC) controller 17
SHA-3 Device Architecture 18
SHA-3 Device Architecture 19
SHA-3 Device Architecture 20
SHA-3 Device Architecture 21
Outline ● Motivation ● Hardware Structure for Trusted Execution Environments ● Boot Procedure with Crypto-accelerators ● Implementation Results ● Conclusions 22
SoC Memory Map 0x00000000 Debug ROM - Boot Procedure Reset Vector ZSBL Calculate Generate Copy BBL Generate SHA3 Keypair from SD Signature (H s ) (S K ,P K ) Devices UART SPI: Contains SD Card BBL RAM SHA3 ED25519 Crypto Sign Acc 0xFFFFFFFF ED25519 RISC-V Processor Base Mult M-mode 23
Boot Procedure 0x00000000 Debug ROM - Boot Procedure Reset Vector ZSBL Calculate Generate Copy BBL Generate SHA3 Keypair from SD Signature (H s ) (S K ,P K ) Devices UART SPI: Contains SD BBL The BBL is copied to Card BBL the main memory SM from a untrusted SHA3 source (SD card). Free This also creates the Mem ED25519 Crypto Secure Monitor ( SM ) Sign Acc 0xFFFFFFFF ED25519 RISC-V Processor Base Mult M-mode 24
Boot Procedure 0x00000000 Debug ROM - Boot Procedure Reset Vector ZSBL Calculate Generate Copy BBL Generate SHA3 Keypair from SD Signature (H s ) (S K ,P K ) Devices UART Payload SPI: Contains SD BBL Card BBL The BBL is hashed SM using the SHA-3 SHA3 hardware by Free pushing registers to Mem ED25519 Crypto the device. Sign Acc 0xFFFFFFFF ED25519 RISC-V Processor Base Mult M-mode 25
Boot Procedure 0x00000000 Debug ROM - Boot Procedure Reset Vector ZSBL Calculate Generate Copy BBL Generate SHA3 Keypair from SD Signature (H s ) (S K ,P K ) Devices UART SPI: Contains SD BBL Card BBL The previous hash is SM used by the SHA3 ED25519 base-point Free Hash (H s ) multiplier to create Mem ED25519 Crypto the Keypair (S K ,P K ) Sign Acc 0xFFFFFFFF ED25519 RISC-V Processor Base Mult M-mode 26
Boot Procedure 0x00000000 Debug ROM - Boot Procedure Reset Vector ZSBL Calculate Generate Copy BBL Generate SHA3 Keypair from SD Signature (H s ) (S K ,P K ) Devices UART SPI: Contains SD BBL Card BBL The Keypair and Auxiliar some auxiliar SM Hashes SHA3 hashes are used to Sign calculate the ED25519 Crypto signature. Sign Acc 0xFFFFFFFF ED25519 Keypair RISC-V Processor Base Mult (S K ,P K ) M-mode 27
Outline ● Motivation ● Hardware Structure for Trusted Execution Environments ● Boot Procedure with Crypto-accelerators ● Implementation Results ● Conclusions 28
Implementation Results Table 1: Synthesis result on Stratix-IV GX Altera FPGA. SHA-3 RocketTile ALUTs 8108 24332 FFs 2790 15325 RAM Bits 0 17680 DSP 0 32 Total 10898 57369 Logic Utilization 3.4% 12.4% RAM Utilization 0% 1% DSP Utilization 0% 2.4% 29
Implementation Results Figure 1: Comparison between software and hardware with different bootloader sizes. Table 2: Execution results for Ed25519 task. 2MB Bootloader Software HW SHA-3 with SW Ed25519 Ed25519 keypair (ms) 109.5 93.4 Ed25519 signature (ms) 231019 82.6 30
Outline ● Motivation ● Hardware Structure for Trusted Execution Environments ● Boot Procedure with Crypto-accelerators ● Implementation Results ● Conclusions 31
Conclusions ● We presented a system platform for trusted execution environments (TEEs) featuring the SHA-3 accelerator. ● ISC-V core with RV64IMAFDC ISA using the Rocket chip generator. ● The SHA-3 accelerator hashes data using a 64-bit register as input. ● The software authenticates the bootloader and utilizes the accelerators. ● The execution time drops significantly compared to software. 32
Questions? 33
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