Team 1803 - 3 level Inverter 1700V Switching JOHN BROUSSEAU(EE), - - PowerPoint PPT Presentation
Lenze Americas Team 1803 - 3 level Inverter 1700V Switching JOHN BROUSSEAU(EE), DANIEL DABKOWSKI(EE), YUANSONG LIU(EE) ADVISOR: PROFESSOR BAZZI Outline Background on Inverters Problem Statement Specifications and Require
JOHN BROUSSEAU(EE), DANIEL DABKOWSKI(EE), YUANSONG LIU(EE) ADVISOR: PROFESSOR BAZZI
Background on Inverters Problem Statement Specifications and Require Approach Capacitive Coupling Logic Based Approach Mixed Approach Simulation Results Hardware Results Upcoming Plans Timeline
A power inverter is an electronic device that performs DC to AC
conversion
A three-phase, two-level inverter varies the line to line output
voltage between Vdc, -Vdc, and 0
A three-phase, three-level inverter can vary the output between
Vdc, Vdc/2, 0, -Vdc/2, and -Vdc
Two level inverter output Three level inverter output
Some parts of Canada and the United States use
600 Vrms systems
Inverters designed for this market normally used 1400 V
transistors
These Transistors are being phased out Nearest equivalents are 1200 V and 1700 V transistors 1700 V transistors do not switch fast enough for the
application
1200 V transistors will fail due to high voltage stress
Lenze wants to use a 3 level inverter topology to do two level switching Transistors would be paired, and switched together as a two level inverter The transistors share the load These transistors do not have the same turn on and turn off characteristics They may still experience
$2000 budget for this project, main cost will be power
MOSFETs ~$5 each, and PCB
Simulation of 600 VRMS (850VDC) 3 HP three level
inverter: characterize losses, select components, find
Scaled down simulation to 240 VRMS (340 VDC) 3 HP Physical PCB, 240 VRMS input, 3 HP, interface with a
provided Lenze Variable Frequency Drive
Ideal case involves two series
MOSFETs switching simultaneously and evenly balancing the DC voltage, with both having on On-State VDS of VDC/2
In practice, this is a concern
because each transistor will have slightly different characteristics, such as internal capacitances
This will cause the transistors to
have different turn-on and turn-off times, which can cause excessive voltage stress across an individual transistor
Utilizes one gate drive signal to power a stack of series
MOSFETs, two in our case
When all transistors are off, the external resistors divide the
voltage load to not exceed the voltage rating of any one transistor
Bottom transistor is switched on, which reverse biases the
diode, causing the gate-source voltage of M2 to be set by a capacitive division of C2 and internal gate-source capacitance of M2, which turns on M2, process repeats for each transistor in the stack
Turn-off is opposite, C2 and internal gate-source
capacitance of M2 drain and turn off the transistor, which then happens for every other transistor in the stack
Benefit of simplicity and few parts
Use solid state components to introduce
additional switching logic
Sequence the transistors such that they do not
go into overvoltage states
A combination of logic statements (Top) will
switch the transistors through a series of states (bottom) where there is never more than two on at one time
Benefits: No risk of overvoltage, always know
which transistors will turn on or off next
Drawbacks: Slower that switching simultaneously,
several additional parts
A = (NOT C) AND S1 B = (NOT D) AND ((NOT C) OR S1) C = (NOT A) AND ((NOT B) OR S2) D = (NOT B) AND s2
determine if the inverter gates should be run in logic-control mode, or through capacitively coupled method
problem involving slew rates
Logic Power MOSFETs Controls
Good Voltage balancing across both transistors Minor turn-on transients
Both are equal Top +20% Bottom -20% Top -20% Bottom +20% Max Vds Top 248 243 245 Max Vds bottom 226 226 226
Using Simulink, we tested
what happened when one transistor consistently switched slower than the
Normally, each transistor
0 V
During each cycle, one
transistor spiked to VDC, as expected
Once the additional
switching logic was added, the transistors switched on and off in the desired sequence (Top)
Additionally, the
sequenced switching had the desired effect of eliminating voltage spikes (Bottom)
Finish hardware testing for capacitive coupling and logic based
method
Finish simulation of mixed approach to determine feasibility Purchase parts for three-phase, three-level inverter topology