Click to edit Master title style A 32nm SoC Platform Technology with 2 nd Generation High-k/Metal Gate Transistors Optimized for Ultra Low Power � Click to edit Master text styles ─ Second level � Third level C.-H. Jan, M. Agostinelli, M. Buehler, Z.-P. Chen, S.-J. Choi, G. Curello, H. � Fourth level Deshpande, S. Gannavaram, W. Hafez, U. Jalan, M. Kang, P. Kolar, K. Komeyli, � Fifth level A. Lake, N. Lazo, S.-H. Lee, T. Leo, J. Lin, N. Lindert, S. Ma, L. McGill, C. Meining, A. Paliwal, J. Park, K. Phoa, I. Post, N. Pradhan, M. Prince, A. Rahman, J. Rizk, L. Rockford, G. Sacks, H. Tashiro, C. Tsai, P. Vandervoorn, J. Xu, L. Yang, J.-Y. Yeh, J. Yip, K. Zhang, P. Bai Logic Technology Development Technology Manufacturing Group Intel Corporation Chia-Hong Jan/ IEDM ‘09, Baltimore, MD Chia-Hong Jan/ IEDM ‘09, Baltimore, MD 1 1 Dec. 9th, ‘09 Dec. 9th, ‘09
Outline Click to edit Master title style 32 nm High-k/Metal Gate SoC Technology � Click to edit Master text styles ─ Second level 32 nm SoC Transistor Architecture � Third level 32 nm SoC Interconnects and Passives � Fourth level � Fifth level 32 nm SoC Embedded Memory Summary Chia-Hong Jan/ IEDM ‘09, Baltimore, MD Chia-Hong Jan/ IEDM ‘09, Baltimore, MD 2 2 Dec. 9th, ‘09 Dec. 9th, ‘09
32 nm High-k/Metal Gate Transistor 32 nm High-k/Metal Gate Transistor Click to edit Master title style � 2 nd gen high-k/metal gate � Click to edit Master text styles � Replacement Metal Gate (RMG) Flow ─ Second level � Third level � 4 th gen strained silicon Meta Me tal G l Gate te � Fourth level � Fifth level � 20% performance improvement over High-k High-k 45 nm high-k/metal gate Silicon Silicon � In high volume manufacturing SiGe SiGe production of multi-core CPU products in multiple fabs Chia-Hong Jan/ IEDM ‘09, Baltimore, MD Chia-Hong Jan/ IEDM ‘09, Baltimore, MD 3 3 Dec. 9th, ‘09 Dec. 9th, ‘09
Replacement Metal Gate (RMG) SOC Flow Replacement Metal Gate (RMG) SOC Flow Click to edit Master title style CPU Flow SOC Flow � Click to edit Master text styles Isolation (wells, Vt) ─ Second level � Third level Dielectric growth � Fourth level Poly-Si dep Poly-Si patterning � Fifth level Logic S/D extension- HP/LP Spacer dep/patterning S/D formation Poly-Si Gate Removal Metal Gate Replacement Contact Formation SoC process flow is derived from the 2 nd generation CPU RMG (Replacement Metal Gate) flow Chia-Hong Jan/ IEDM ‘09, Baltimore, MD Chia-Hong Jan/ IEDM ‘09, Baltimore, MD 4 4 Dec. 9th, ‘09 Dec. 9th, ‘09
Outline Click to edit Master title style 32 nm High-k/Metal Gate SoC Technology � Click to edit Master text styles ─ Second level 32 nm SoC Transistor Architecture � Third level 32 nm SoC Interconnects and Passives � Fourth level � Fifth level 32 nm SoC Embedded Memory Summary Chia-Hong Jan/ IEDM ‘09, Baltimore, MD Chia-Hong Jan/ IEDM ‘09, Baltimore, MD 5 5 Dec. 9th, ‘09 Dec. 9th, ‘09
Triple Transistor Architecture Triple Transistor Architecture Click to edit Master title style Logic Low Power HV I/O Transistor Transistor Transistor � Click to edit Master text styles (HP or SP) (LP) (1.8 V/2.5 V or 3.3 V) ─ Second level � Third level � Fourth level � Fifth level � A low cost implementation with three types of transistors “co-exist” on the same die: � Logic (HP or SP) Logic (HP or SP) : for burst CPU performance � Low Po Low Powe wer (LP) r (LP) : for always-on-always-connected application and long battery life � HV I/O HV I/O: for high voltage I/O � Take advantage of the low gate leakage of high-k/metal gate to avoid the traditional expensive “triple gate” approach Chia-Hong Jan/ IEDM ‘09, Baltimore, MD Chia-Hong Jan/ IEDM ‘09, Baltimore, MD 6 6 Dec. 9th, ‘09 Dec. 9th, ‘09
Transistors Summary Transistors Summary Click to edit Master title style Logic HV I/O Transistor Low Power Type (option for HP or SP) (option for 1.8 or 3.3 V) � Click to edit Master text styles HP SP LP 1.8/2.5 V 3.3V ─ Second level EOT (nm) 0.95 0.95 0.95 ~ 4 ~ 7 � Third level .75/ 1 .75/ 1 0.75/1.2 1.5 /1.8 1.5 /3.3 Vdd (V) � Fourth level 112.5 112.5 126 min. 338 min. 450 Pitch (nm) � Fifth level 30 34 46 >140 >300 Lgate (nm) NMOS Idsat 1.53 1.12 0.71 0.68 0.7 @ 1 V @ 1 V @ 1 V @1.8 V @3.3 V (mA/um) PMOS Idsat 1.23 0.87 0.55 0.59 .6 @ 1V @ 1 V @ 1 V @1.8 V @3.3 V (mA/um) Ioff (nA/um) 100 1 0.03 0.1 <0.01 Tightest minimum gate pitch for 32/28 nm processes Chia-Hong Jan/ IEDM ‘09, Baltimore, MD Chia-Hong Jan/ IEDM ‘09, Baltimore, MD 7 7 Dec. 9th, ‘09 Dec. 9th, ‘09
Logic and LP Transistors Dynamic Range Logic and LP Transistors Dynamic Range Click to edit Master title style � Click to edit Master text styles ─ Second level 10,000 x � Third level � Fourth level � Fifth level Logic and LP transistors cover 4 orders of magnitude (10,000 x) of leakage power to support a wide dynamic range SoC applications Chia-Hong Jan/ IEDM ‘09, Baltimore, MD Chia-Hong Jan/ IEDM ‘09, Baltimore, MD 8 8 Dec. 9th, ‘09 Dec. 9th, ‘09
Logic Transistors Ion-Ioff (HP/SP) Logic Transistors Ion-Ioff (HP/SP) Click to edit Master title style � Click to edit Master text styles ─ Second level � Third level � Fourth level � Fifth level � Highest reported drives for 32/28 nm SoC process at tightest gate pitch (112 nm) -1.53 mA/um (N) / 1.12 mA/um (P) at 100nA/um � 20-35% improvement over 45 nm high-k/MG logic transistors Chia-Hong Jan/ IEDM ‘09, Baltimore, MD Chia-Hong Jan/ IEDM ‘09, Baltimore, MD 9 9 Dec. 9th, ‘09 Dec. 9th, ‘09
Logic/LP Transistors Vt vs. L Logic/LP Transistors Vt vs. L Click to edit Master title style � Click to edit Master text styles ─ Second level � Third level � Fourth level � Fifth level � Short channel effect, DIBL, Vt roll-off are well controlled � SP Vt < 400 mV, LP Vt ~ 500 mV Chia-Hong Jan/ IEDM ‘09, Baltimore, MD Chia-Hong Jan/ IEDM ‘09, Baltimore, MD 10 10 Dec. 9th, ‘09 Dec. 9th, ‘09
Logic Transistor I-V Characteristics Logic Transistor I-V Characteristics Click to edit Master title style Sub-threshold Id-Vd Characteristics � Click to edit Master text styles ─ Second level � Third level � Fourth level � Fifth level � Well controlled transistor I-V characteristics – HP and SP � Sub-threshold slope ~ 100mV/decade (HP), < 90 mV/decade (SP) � DIBL – SP: 90 mV (N)/100 mV (P); HP: 130 mV (N)/140 mV (P) Chia-Hong Jan/ IEDM ‘09, Baltimore, MD Chia-Hong Jan/ IEDM ‘09, Baltimore, MD 11 11 Dec. 9th, ‘09 Dec. 9th, ‘09
Low Power Transistors Ion-Ioff (LP) Low Power Transistors Ion-Ioff (LP) Click to edit Master title style � Click to edit Master text styles ─ Second level � Third level � Fourth level � Fifth level � Highest reported drive currents at lowest standby leakage (30pA/um, 1000x lower than HP) AND � Low active power (0.75 V) with good performance Chia-Hong Jan/ IEDM ‘09, Baltimore, MD Chia-Hong Jan/ IEDM ‘09, Baltimore, MD 12 12 Dec. 9th, ‘09 Dec. 9th, ‘09
Low Power Transistor I-V Characteristics Low Power Transistor I-V Characteristics Click to edit Master title style Sub-threshold Id-Vd Characteristics � Click to edit Master text styles ─ Second level � Third level � Fourth level � Fifth level � Well controlled transistor I-V characteristics - LP � Sub-threshold slope ~ < 85 mV/decade � DIBL - 70 mV (N)/100 mV (P) Chia-Hong Jan/ IEDM ‘09, Baltimore, MD Chia-Hong Jan/ IEDM ‘09, Baltimore, MD 13 13 Dec. 9th, ‘09 Dec. 9th, ‘09
Low Power Transistors Total Leakage Total Leakage Low Power Low Power Transistors Total Leakage Click to edit Master title style � Click to edit Master text styles ─ Second level � Third level I gate ( on) � Fourth level On State � Fifth level I gate ( off) I off I junction I LKG = ½ ( “ON” State Leakage ) + ½ (“OFF” State Leakage ) Off State = ½ ( I gate (ON) ) + ½ (SF x I off + I junc + I gate (OFF) ) All leakage components – Ioff, Igate(on), Igate(off) and Ijunction need to be mitigated for low power transistor Chia-Hong Jan/ IEDM ‘09, Baltimore, MD Chia-Hong Jan/ IEDM ‘09, Baltimore, MD 14 14 Dec. 9th, ‘09 Dec. 9th, ‘09
High Voltage Transistors (1.8/2.5 V or 3.3 V) High Voltage Transistors (1.8/2.5 V or 3.3 V) Click to edit Master title style � Click to edit Master text styles � 2 nd gen high-k/metal gate I/O ─ Second level Metal Gate Transistors � Third level SiGe SiGe � Fourth level � 1.8/2.5 V or 3.3 V options High-k � Fifth level � High-k/Oxide composite gate stack � Min gate length = 140 nm (1.8 V) Min gate length = 300 nm (3.3 V) Chia-Hong Jan/ IEDM ‘09, Baltimore, MD Chia-Hong Jan/ IEDM ‘09, Baltimore, MD 15 15 Dec. 9th, ‘09 Dec. 9th, ‘09
Reliability – Logic and High Voltage Reliability – Logic and High Voltage Click to edit Master title style � Click to edit Master text styles ─ Second level � Third level � Fourth level � Fifth level Robust NMOS and PMOS high k + metal gate logic and I/O transistors TDDB Chia-Hong Jan/ IEDM ‘09, Baltimore, MD Chia-Hong Jan/ IEDM ‘09, Baltimore, MD 16 16 Dec. 9th, ‘09 Dec. 9th, ‘09
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