Synthesis of Low Po y ower Clock Trees for Handling Power ‐ s supply Variations Shashank Bujimalla and Cheng ‐ Kok Koh School of Electrical and School of Electrical and Computer Engineering Computer Engineering Purdue U niversity 1
Out Out line line Clock distribution networks a and challenges Problem definition Parameters affecting clock sk kew in clock trees Analyze the parameters, varia tions and their effect on clock skew. Propose techniques to reduce e the clock skew. Our approach Experimental setup and Resu ults Conclusions 2
Clock distribut tion networks Challenges of clock network synt hesis Satisfy clock skew constraints i n the presence of variations. Reduce the power dissipated. ( (Metric: Capacitance.) ) Popular structures Popular structures Clock trees ‐ Relatively low var riation ‐ tolerance, Low capacitance. Clock meshes ‐ High variation ‐ t Clock meshes ‐ High variation ‐ t tolerance High capacitance tolerance, High capacitance. Hybrid (mesh + tree, tree + cro oss ‐ links) Focus of our work: Clock tree stru uctures Analyze the parameters and va ariations affecting clock skew. Propose techniques to reduce the clock skew. 3
Problem d definition Termin nology Local sink pairs L l i k i Sink pairs closer than a specifie ed distance ( L ). L : Local skew distance L : Local skew distance. Local clock skew (LCS) Clock skew between any local s sink pair. Maximum local clock skew (MLCS S) Many such local sink pairs. Maximum LCS among them. 4
Problem d definition Based on ISPD 201 Based on ISPD 201 10 contest problem 10 contest problem Given Clock source, sink and blockage lo Cl k i k d bl k l ocations. i Local skew distance, L. MLCS limit . MLCS limit . Slew limit . Inverter and wire library. Power ‐ supply and wire ‐ width var riations (Uniform distribution). Construct a low capacitance (power C t t l it ( ) l ) clock tree k t Satisfy slew constraint: Signal sle ew < Slew limit . Satisfy blockage constraint: Inve Satisfy blockage constraint: Inve erters cannot be placed over blockages. erters cannot be placed over blockages. Satisfy MLCS constraint: 95 th per rcentile of MLCS, MLCS 95% < MLCS limit . 5
Parameters affec cting clock skew Clock skew parameters Number of sinks, N . Number of sinks, N . Number of buffer levels, B . Delay variation per buffer stage, σ σ 0 . ‐ Buffer stage = Buffer + Interconnec ct it drives. ‐ σ 0 is the standard deviation of del ay per buffer stage. Buffer stage 6
Parameters affec cting clock skew Clock skew un Clock skew un der variations der variations Clock tree T D Identical path delays from source to sinks. ‐ Normal distribution with same mea an and variance. Possible overlapping paths. Clock skew is R D . Clock skew is R D . Clock tree T I (Hypothetical) I Similar to T D . Assume: No overlapping paths. Clock skew is R Clock skew is R I . P ( R D < z ) ≥ P ( R I < z ) ( ) ( ) => E ( R I ) ( I ) ≥ E ( R D ) ( D ) (from [4] and [5]) ( [ ] [ ]) D I P ( R D < z ) ≥ P ( R I < z ) => R I, 95% ≥ R D, 95% R D, 95% = α α . R I, 95% (where 0 ≤ α ≤ 1) [4] Kugelmass et al., “Probabilistic model for clock skew w”, Proc. Intl Conf Systolic Arrays , 1988. [5] Kugelmass et al., “Upper bound on expected clock skew”, IEEE Trans. Computers , 1990. 7
Parameters affec cting clock skew Clock skew un der variations R D, 95% = α . R I, 95% R = α R (where 0 ≤ α ≤ (where 0 ≤ α ≤ ≤ 1) ≤ 1) Asymptotic formulae for E ( R I ) and Va ar ( R I ) . (from [4] and [5]) ‐ For given N , B and σ 0 . Sample set large => Assume normal distribution for R I . R I, 95% � E ( R I ) + 2 . √ Var ( R I ) R D, 95% � α . [ E ( R I ) + 2 . √ Var ( R I ) ] √ Formula for 95 th percentile of clo Formula for 95 th percentile of clo ock skew ( R ) for general clock tree ock skew ( R ) for general clock tree. Include nominal clock skew ( NCS ). R 95% � NCS + α . [ E ( R I ) + 2 . √ Var ( R I ) [ ( I ) ( I ) ] 95% Empirically estimate α . 8
Parameters af ffecting MLCS Wire ‐ width variations (vs) Power ‐ ‐ supply variations Low slew => Small DC ‐ connected su Low slew > Small DC connected su ubtrees. ubtrees. Effect of wire variations relatively sm mall compared to power ‐ supply variations . Our focus: Power ‐ supply variation ns Delay variation per buffer stage, σ 0 : ‐ σ of buffer stage � σ of buffer σ 0 of buffer stage σ 0 of buffer. DC-connected subtree 9
Parameters af Parameters af ffecting MLCS ffecting MLCS LCS parameters Number of buffer levels, B : ‐ Subtree of the NCA (nearest comm on ancestor) of local sink pair. Number of sinks N : Number of sinks, N : ‐ Subtree of the NCA of local sink pai ir. ‐ Number of level 1 buffers (bottom ‐ up from sinks). NCA MLCS parameters MLCS t σ 0 , N and B values that give the highest 95% LCS among all local g g N sink pairs. 10
Parameters af ffecting MLCS Power ‐ supp ply variations ISPD 2010 contest ISPD 2010 contest Inverter modeled as a single point. Many inverters can be placed at a sin ngle location. ‐ Parallel inverters to increase the dr rive strength. ‐ Buffers. Types of Monte ‐ Carlo (MC) simul lations ISPD MC simulations . (ISPD problem m.) ‐ Inverters placed at same location c could get different voltages. ‐ Same as the contest simulations. SLSV MC simulations (SLSV problem SLSV MC simulations . (SLSV problem m.) m ) ‐ Inverters placed at same location g get identical voltages. ‐ SLSV : Single Location Single Voltag ge. 11
Observati ons on σ 0 Key Technique ‐ ISPD problem Use parallel inverters to reduce σ σ 0 : Note: Short circuit power dissipation co ould increase. ‐ Not captured if only capacitance Not captured if only capacitance is used as metric for power dissipation. is used as metric for power dissipation. 12
Observati ons on σ 0 Key Techniques Key Techniques ‐ SLSV problem SLSV problem Buffers (chain of 2 inverters) have low wer σ 0 than inverters. Inverters of a buffer (chain of 2 in nverters) get identical power ‐ supply voltages. Use buffers (chain of 2 inverters) Use buffers (chain of 2 inverters). . Lower buffer input slew => Lower σ 0 . Try to maintain low slew in the clo ock tree. No significant change in σ 0 for differe N i ifi t h i f diff ent buffer sizes. t b ff i At low input slews. For loads at which buffers are ins For loads at which buffers are ins erted to avoid slew constraint erted to avoid slew constraint violations. In our work: A single buffer size is u sed in entire clock tree (for simplicity). 13
Observations s on N and B Key Tech hniques However buffer size determi However, buffer size determi ines N and B. ines N and B ISPD and SLSV problem. Lower values of N and B => L Lower MLCS 95% . Difficult to estimate the buffer Diffi lt t ti t th b ff r size that gives lower N and B . i th t i l N d B ‐ Non ‐ uniform sink distributio n. ‐ Blockages. ‐ Blockages ‐ Drive strength (vs) Upstream m capacitance presented. We perform a linear search to We perform a linear search to find the desired buffer size. find the desired buffer size. 14
Our ap Our ap proach proach Given a buffer size Construct low nominal skew c clock tree Deferred Merge Embedding (DM ME) algorithm Merging strategy Merging strategy Buffer insertion strategy ‐ Avoid slew and blockage con nstraint violations Buffer modeling Use the formula for R 95% to es U th f l f R t stimate MLCS 95% ti t MLCS 15
Our app proach Buffer m B ff modeling d li Use fast buffer modeling from [6] with minor modification. Iterative approach to model buffer Iterative approach to model buffer. Use NGSPICE for buffer modeling. . Stringent MLCS constraints. [6] R.Puri et al., “Fast and accurate wire delay estimati on for physical synthesis of large ASICs”, in Proc. GLSVLSI , 2002. 16
Our ap proach Two s stages t Stage 1 : Perform a linear search for r the desired buffer size Gi Given a buffer size b ff i Construct low nominal skew tree ( (DME algorithm) Reason: Merging Using NGSPICE while Buffer insertion strategy searching for desired ‐ Avoid slew and blockage cons straint violations buffer size ‐ Buffer modeling (Use fast buffe Buffer modeling (Use fast buffe er modeling) er modeling) Expensive! Use the formula for R 95% to estima ate MLCS 95% Stage 2 : Construct low nominal skew w tree (use buffer size determined d from stage 1) Similar to above EXCEPT Buffer modeling (use NGSPICE) ) Fine tune nominal clock skew ( Fine tune nominal clock skew ( use NGSPICE) use NGSPICE) 17
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