Stress-Aware Routing to Mitigate Aging Effects in SRAM-based FPGAs - PowerPoint PPT Presentation

Stress-Aware Routing to Mitigate Aging Effects in SRAM-based FPGAs 𝟑𝟕 𝐮𝐢 International Conference on Field- Programmable Logic and Applications Lausanne, Switzerland, Aug. 29 th – Sep. 2 nd , 2016 Behnam Khaleghi 𝟐 , Behzad Omidi 𝟐 , Hussam Amrouch 𝟑 , Joerg Henkel 𝟑 and Hossein Asadi 𝟐 1 Sharif University of Technology, Iran 2 Karlsruhe Institute of Technology, Germany

Nano-CMOS Challenges Nano-CMOS Era Area & Reliability Power Cost   Density  External Implementation Component Disturbances Mistakes Defects Lightning, Radiations, Wear-out, Aging Temperature etc. Noise etc. 2/23

Basic Concepts: Aging Phenomenon  Aging + + + |𝑊 𝑕𝑡 | = 𝑊𝑒𝑒 + + |𝑊 𝑕𝑡 | = 0 - - H H H  Bias Temperature Instability (BTI) Si Si Si Source(p) Drain(p)  Negative BTI pMOS type  Positive BTI nMOS type  Hot Carrier Induced Degradation (HCID) 𝑊 𝑕  Negative HCID pMOS type 𝑊 𝑒 𝐽 𝑕𝑏𝑢𝑓  Positive HCID nMOS type - - - 𝐽 𝑑ℎ𝑏𝑜𝑜𝑓𝑚 Source(n) Drain(n)  Other types: 𝐽 𝑐𝑣𝑚𝑙  Time Dependent Dielectric Breakdown  Electro migration 3/23

Basic Concepts: BTI Remove Voltage  Bias Temperature Instability Threshold Voltage Stress Recovery  Includes two phases:  Stress time  Applied voltage to Gate of MOS 𝑊 𝑕𝑡 = 𝑊 𝑒𝑒  Threshold voltage ↑   Recovery time Time  Remove voltage to Gate of MOS 𝑊 𝑕𝑡 = 0  Threshold voltage ↓   Ideal Duty Cycle (DC) = 0.5  Attention: ∆𝑾 𝒖𝒊 𝑺𝒇𝒅𝒑𝒘𝒇𝒔𝒛−𝑼𝒋𝒏𝒇 < ∆𝑾 𝒖𝒊 𝑻𝒖𝒔𝒇𝒕𝒕−𝑼𝒋𝒏𝒇 𝑇. 𝐿𝑗𝑏𝑛𝑓ℎ𝑠, 𝐵. 𝐵𝑛𝑝𝑣𝑠𝑗, 𝑏𝑜𝑒 𝑁. 𝐶. 𝑈𝑏ℎ𝑝𝑝𝑠𝑗, Investigation of nbti and pbti induced aging in different lut implementations, 𝐽𝑜 𝐽𝑜𝑢𝑚. 𝐷𝑝𝑜𝑔𝑓𝑠𝑓𝑜𝑑𝑓 𝑝𝑜 𝐺𝑗𝑓𝑚𝑒 − 𝑄𝑠𝑝𝑕𝑠𝑏𝑛𝑛𝑏𝑐𝑚𝑓 𝑈𝑓𝑑ℎ𝑜𝑝𝑚𝑝𝑕𝑧 (𝐺𝑄𝑈), 2011 . 4/23

Basic Concepts: BTI Impacts  Negative Effects of BTI I D Reduction Timing Delay Increase (I d ∝ V dd − Vth) Violation V th Shift Transient & Critical Charge Soft Error Permanent Reduction Sensitivity Fault 5/23

Motivation: FPGA Susceptibility  FPGA High Susceptibility to Aging I 1 SRAM I 2  Circuit varies with each new reconfig. I3 Output LUT Mux  Both logic and configuration memory Flip-  Configuration memory  permanent fault In Flop c  Too many resources to monitor N n N 1 . . . LB CB LB CB LB Logic: 20%-30% Routing: 80%-70% CB SM CB SM CB W 1 E 1 . . . . LB CB LB CB LB Aging in Routing . . W n E n more Challenging. SM SM CB CB CB LB CB LB CB LB S 1 . . . S n 6/23

Motivation: Routing Vulnerability Routing 1 Routing 0 LUT 1 LUT 0 20 x 10000 Flash Translation 15 Layer Algorithm 10 5 in SSD Controllers 0 (Min size Virtex-II)  𝑄 𝑡𝑢𝑠𝑓𝑡𝑡 (𝑆𝑝𝑣𝑢𝑗𝑜𝑕) ≈ 𝑄 0→0 + 𝑄 1→1 = 0.92 × 0.92 + 0.08 × 0.08 = 0.85  𝑄 𝑡𝑢𝑠𝑓𝑡𝑡 (𝑀𝑉𝑈) ≈ 𝑄 0→0 + 𝑄 1→1 = 0.41 × 0.41 + 0.59 × 0.59 = 0.52 7/23

Motivation: Routing Vulnerability  Routing SRAMs are within Circuit Critical Path  Not for LUTs PG-Mux PG-Buffer PG-Combined TMG-Mux TMG-Buffer TMG-Combined Aging Induced Delay LUT 18% 16% 14% 12% 10% 8% 6% 4% 2% 0% 0 1 2 3 4 5 6 7 8 9 10 Year LUT SB MUX 8/23

Proposed Method: Duty Cycle  Optimal Duty Cycle  SRAM DC = 0.5  So, associated SB transistor 9/23

Proposed Method: Reconfigurations  Configuration Cells in Consecutive Reconfigurations  Invertible  0 → 1 Overlapping 0 Prev.0 Noninvertible New.1 Zero New.0 Overlapping 1 Prev.1  1 → 0 10/23

Proposed Method: Base Architecture  FPGA Architecture and Structures in Proposed Method Bi (top) & Uni- Bi (top) & Uni- Island-Style Directional SM Directional SB Architecture (bottom) (bottom) 11/23

Proposed Method: Cell Inversion  Switch-Box: Buffer Based 1 0 0 0  Direct path enabling 1 0 1 0 0 0 1 0 1 0 0 1 0 0 12/23

Proposed Method: Cell Inverting 1 0  Switch-Box: Multiplexer Based  Hamming distance concept 1 0 1 1 6 Transistors Inverted 2 SRAMs Inverted 0 Hotspot Transistor 0 0 4 Transistors Inverted 4 Transistors Inverted 1 SRAM Inverted 1 SRAM Inverted 1 Hotspot Transistor 2 Hotspot Transistors 13/23

Proposed Method Scheme 2 Scheme 1  Routing by Assigning Higher Cost  Routing by Avoiding Using to Previous Used Cells Previous Active (0 or 1) Cells  Inverting All Unused Cells  Inverting All Unused Cells Proposed Method  Assigning Initial Cost for (prev.) Active SRAMs  Overlaping SRAM > Threshold → Use Scheme 1  Overlaping SRAM < Threshold → Use Scheme 2 14/23

Proposed Method: Overall Flow Start No Reduce the Cost Routing Succeeded? of Config prev Read Previous Configuration ( Config prev ) Yes Read Overlapping Configuration Invert Unused Cells of (Config overlap ) New Design(0 → 1)∗ Yes Undo Cost ← Assign_Priority (Mux i ∈ Config prev ) Improper Connection? Inverted bits No No No Config overlap < threshold All Unused Cells Checked? Yes Yes Update New Design’s Mux i ← invert(Mux i ∈ Config overlap ) Configuration End * Unconditional 1  0 inverting 15/23

Proposed Method: Threshold Value alu4 apex2 apex4 bigkey clma (used configuration bits) des diffeq dsip elliptic ex5p ex1010 frisc misex3 pdc s298 Shared Cells s38417.1 s38581 seq spla tseng Placing 100 90 Benchmarks with 80 70 60 Different Seed 50 40 Numbers 30 20 10 0 (used configurations bit) 1 2 3 4 5 6 7 8 9 10 11 # of Reconfigurations with Different Placements 100 Shared Cells 100 100 90 80 Average 70 60 Overlapping 50 40 23.8 Configuration Bit 30 20 7.7 2.9 1.2 0.5 0.2 10 0.1 0.05 0.02 0.01 0 1 2 3 4 5 6 7 8 9 10 11 # of Reconfigurations with Different Placements 16/23

Experimental Setup Tools Architecture Island Style Aging Impact HSpice Measurement Uni and Bi SB Type Clustering, Placement Directional VPR 7.0 and Routing Switch Matrix Subset Topology Devices Buffer/ SB Structure Logic Array Minimum Multiplexer Routing Channel Wire Segment 1.2x Min. L=1 Width Length 17/23

Experimental Setup (cont.)  Assumption  Circuits reconfigured in identical time intervals  Same Circuit is Reconfigured  Using different placement seeds  FPGA array size and channel width is maintained  Same circuit with different placement and routing  Analogous to using different circuits  VPR tool modified to generate bitstream after routing each circuit 18/23

Results  Stress Time Reduction (Duty Cycle) Mux-Conv Mux-Proposed Buffer-Conv Buffer-Proposed 1.0 ycle y Cyc 40% Mux-based 0.5 Duty 41% Buffer-based 0.0  Hot Spot Elimination (Required Reconfigurations) Mux-Conv Mux-Proposed Buffer-Conv Buffer-Proposed ion 15 iguratio 10 63% Mux-based nfig Reconf 5 57% Buffer-based 0 19/23

Results (cont.)  Aging Induced Delay (Average) Base 3year Proposed 3year Base 10year Proposed 10year Aging Induced 10% Delay 3 years 8.7% 3 years (OPT) 11.15% 5% 10 years 17.52% 10 years (OPT) 19.66% 0%  Aging Induced Delay (Worst) 3 years 10 years 20% Improvement 15% 3 years 9.72% 10% 5% 10 years 18.32% 0% 20/23

Results (cont.)  Performance Overhead Frequency (MHz) Mux-Conv Mux-Proposed Buffer-Conv Buffer-Proposed 300 250 200 Mux based 0.2% 150 100 0% Buffer based 50 0  Lifetime Improvement 25 thod Proposed Meth 20 (year) 15 10 5 0 4 5 6 7 8 9 10 Baselin ine lifeti time (year) 21/23

Future Work  Generalization  Commercial FPGA Parameters  SB multiplexer  Size, pass gate vs. transmission, two-level versus tree-based  Wire length  Switch matrix topology  Impact of Temperature Distribution, Process Variation, etc.  Impact on Soft Error Rate 22/23

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