Smart Port Card Version 2 (SPC-II) Architecture William D. - PowerPoint PPT Presentation

Smart Port Card Version 2 (SPC-II) Architecture William D. Richard, Ph.D. Washington wdr@ee.wustl.edu WASHINGTON UNIVERSITY IN ST LOUIS

SPC-II Design Team • William D. Richard Hardware Design • John D. DeHart Integration/Test • Mike Richards Board Layout • Tom Chaney Physical Issues • Ed Spitznagel Kernel Boot Disk • Berkley Shands Kernel Boot Disk • Amy Hawkins FPGA VHDL • Jon Turner Beer? Washington DeHart, Richard- 6/19/2002 2:36 PM 2 WASHINGTON UNIVERSITY IN ST LOUIS

SPC-I Architecture SWITCH OPP IPP FPX System 64 MB FPGA EDO DRAM 16 bit PCI Intel HX APIC North Bridge BUS SPC 16 bit 166 MHz Pentium TI 512 KB L2 Cache Link Washington DeHart, Richard- 6/19/2002 2:36 PM 3 WASHINGTON UNIVERSITY IN ST LOUIS

SPC-I Architecture Addr/Data Ctrl Ctrl North- Cache CPU DRAM Bridge Addr/Data/Ctrl Intel Embedded Module PCI Bus INIT NMI Intr APIC RTC’ PIC PIT UART1 UART1 Interface BIOS ROM Link Interface UART2 UART2 Interface System FPGA Switch Interface Washington DeHart, Richard- 6/19/2002 2:36 PM 4 WASHINGTON UNIVERSITY IN ST LOUIS

SPC-I Architecture Bottom Top Washington DeHart, Richard- 6/19/2002 2:36 PM 5 WASHINGTON UNIVERSITY IN ST LOUIS

SPC-I Architecture Switch Connector Line Card Connector Washington DeHart, Richard- 6/19/2002 2:36 PM 6 WASHINGTON UNIVERSITY IN ST LOUIS

SPC-I Architecture Intel CPU Module Washington DeHart, Richard- 6/19/2002 2:36 PM 7 WASHINGTON UNIVERSITY IN ST LOUIS

SPC-I Architecture EDO DRAM SODIMM Washington DeHart, Richard- 6/19/2002 2:36 PM 8 WASHINGTON UNIVERSITY IN ST LOUIS

SPC-I Architecture APIC Washington DeHart, Richard- 6/19/2002 2:36 PM 9 WASHINGTON UNIVERSITY IN ST LOUIS

SPC-I Architecture System FPGA Washington DeHart, Richard- 6/19/2002 2:36 PM 10 WASHINGTON UNIVERSITY IN ST LOUIS

SPC-I Architecture Serial Ports Washington DeHart, Richard- 6/19/2002 2:36 PM 11 WASHINGTON UNIVERSITY IN ST LOUIS

SPC-II Architecture SWITCH OPP IPP BIOS ISA Super-IO Devices FPX 256 MB ISA Bus SDRAM South Bridge 32 bit 16 bit Port 1 PCI Intel BX FPGA APIC North Bridge BUS Port 0 16/32 bit 16 bit SPC-II 500/700 MHz Pentium-III TI 256 KB L2 Cache Link Washington DeHart, Richard- 6/19/2002 2:36 PM 12 WASHINGTON UNIVERSITY IN ST LOUIS

SPC-II Architecture AGP Bus DRAM Video Video DB15 IDE Bus FLASH DISK I/O Keyboard P-III North- South- Mouse CPU Bridge Bridge BIOS Serial Ports ETX Embedded Module ISA Bus PCI Bus APIC FPGA Switch Interface Link Interface Washington DeHart, Richard- 6/19/2002 2:36 PM 13 WASHINGTON UNIVERSITY IN ST LOUIS

Advantec PIII-500 ETX Module Washington DeHart, Richard- 6/19/2002 2:36 PM 14 WASHINGTON UNIVERSITY IN ST LOUIS

Advantec PIII-500 ETX Module Voltage Regulator Pentium III South Bridge North Bridge AGP Video SODIMM Socket Washington DeHart, Richard- 6/19/2002 2:36 PM 15 WASHINGTON UNIVERSITY IN ST LOUIS

Advantec PIII-500 ETX Module Planar Connectors Washington DeHart, Richard- 6/19/2002 2:36 PM 16 WASHINGTON UNIVERSITY IN ST LOUIS

SPC-II Architecture Top Bottom Washington DeHart, Richard- 6/19/2002 2:36 PM 17 WASHINGTON UNIVERSITY IN ST LOUIS

SPC-II Architecture ETX P-III Top Module Heat Top Spreader Washington DeHart, Richard- 6/19/2002 2:36 PM 18 WASHINGTON UNIVERSITY IN ST LOUIS

SPC-II Architecture Line Card Connector Top Switch Connector Bottom Washington DeHart, Richard- 6/19/2002 2:36 PM 19 WASHINGTON UNIVERSITY IN ST LOUIS

SPC-II Architecture 256 MB SDRAM Top Bottom APIC Washington DeHart, Richard- 6/19/2002 2:36 PM 20 WASHINGTON UNIVERSITY IN ST LOUIS

SPC-II Architecture 32-Bit Top PCI Slot FPGA Bottom Washington DeHart, Richard- 6/19/2002 2:36 PM 21 WASHINGTON UNIVERSITY IN ST LOUIS

SPC-II Architecture Video Top Keyboard Mouse Bottom 32 MB Flash IDE Disk Washington DeHart, Richard- 6/19/2002 2:36 PM 22 WASHINGTON UNIVERSITY IN ST LOUIS

SPC-II Architecture Serial Ports Top Bottom 150 mAH Battery Washington DeHart, Richard- 6/19/2002 2:36 PM 23 WASHINGTON UNIVERSITY IN ST LOUIS

IP Traffic in from Link Normal IP Traffic Active IP Traffic FPX BW fpx 32 bit 16 bit Port 1 FPGA APIC Port 0 16/32 bit BW link TI Link Washington DeHart, Richard- 6/19/2002 2:36 PM 24 WASHINGTON UNIVERSITY IN ST LOUIS

IP Traffic out to Link Normal IP Traffic Active IP Traffic FPX BW fpx 32 bit 16 bit Port 1 FPGA APIC Port 0 16/32 bit BW link TI Link Washington DeHart, Richard- 6/19/2002 2:36 PM 25 WASHINGTON UNIVERSITY IN ST LOUIS

Total Traffic Normal IP Traffic Normal IP Traffic Active IP Traffic Active IP Traffic FPX FPX BW fpx BW fpx 32 bit 32 bit 16 bit Port 1 16 bit Port 1 FPGA APIC FPGA APIC Port 0 Port 0 16/32 bit 16/32 bit BW link BW link TI TI • BW on Link • BW SPC to/from FPX X <= BW link BW fpx = (1-p)X + 3pX BW active = pX = Active Traffic (1-p)X = Normal IP Traffic Washington DeHart, Richard- 6/19/2002 2:36 PM 26 WASHINGTON UNIVERSITY IN ST LOUIS

Total Traffic p BW active BW fpx • BW on Link X <= BW link .1 100Mb/s 1.2 (1-p)X = Normal IP Traffic pX = Active IP Traffic .2 200Mb/s 1.4 • BW SPC to/from FPX .3 300Mb/s 1.6 BW fpx = (1-p)X + 3pX • If .4 400Mb/s 1.8 p = 0.1 .5 500Mb/s 2.0 BW link =1 Gb/s • Then BW fpx <= .9(1Gb/s) + .3(1Gb/s) BW fpx <= 1.2Gb/s Washington DeHart, Richard- 6/19/2002 2:36 PM 27 WASHINGTON UNIVERSITY IN ST LOUIS

SPC II FPGA Architecture Initial Design: SPC-I Mode PCI Bus Port APIC Port 0 Port 1 OSC 16 16 16 16 16 16 16 16 LC FPX Switch SPC-II FPGA Washington DeHart, Richard- 6/19/2002 2:36 PM 28 WASHINGTON UNIVERSITY IN ST LOUIS

SPC II FPGA Architecture Initial Design: Clock Domains PCI Bus Port APIC Port 0 Port 1 OSC 16 16 16 16 16 16 16 16 LC FPX Switch SPC-II FPGA Washington DeHart, Richard- 6/19/2002 2:36 PM 29 WASHINGTON UNIVERSITY IN ST LOUIS

SPC II FPGA Architecture Final Design: Cell Routing Based on VPI/VCI PCI Bus Port APIC Port 0 Port 1 OSC 16 16 16 16 VPI[0]=1 16/32 32 VPI[0]=0 64<=VCI<=127 32 16/32 LC FPX Switch SPC-II FPGA Washington DeHart, Richard- 6/19/2002 2:36 PM 30 WASHINGTON UNIVERSITY IN ST LOUIS

SPC II FPGA Architecture Final Design: Clock Domains PCI Bus Port APIC Port 0 Port 1 OSC 16 16 16 16 VPI[0]=1 16/32 32 VPI[0]=0 64<=VCI<=127 32 16/32 LC FPX Switch SPC-II FPGA Washington DeHart, Richard- 6/19/2002 2:36 PM 31 WASHINGTON UNIVERSITY IN ST LOUIS

SPC II FPGA Architecture Final Design: Remote CPU Reset Via Control Cell PCI Bus Port APIC Port 0 Port 1 OSC 16 16 16 16 Reset VPI[0]=1 VPI[0]=1 VCI = 38 16/32 32 VPI[0]=0 64<=VCI<=127 32 16/32 LC FPX Switch SPC-II FPGA Washington DeHart, Richard- 6/19/2002 2:36 PM 32 WASHINGTON UNIVERSITY IN ST LOUIS

SPC II Relative Performance Packet Forwarding Rates in KP/s 300 250 200 KP/s 150 100 SPC-I/166 SPC-II/500 50 SPC-II/700 0 1 CELL 32 CELL PACKETS PACKETS 88 15.5 SPC-I/166 259 23.2 SPC-II/500 245 23.2 SPC-II/700 Washington DeHart, Richard- 6/19/2002 2:36 PM 33 WASHINGTON UNIVERSITY IN ST LOUIS

SPC II Relative Performance Packet Forwarding Rates in KP/s 300 250 200 KP/s 150 SPC-I/166 100 SPC-II/500 SPC-II/700 50 0 1 CELL (32 BYTE) PACKETS 88 SPC-I/166 259 SPC-II/500 245 SPC-II/700 Washington DeHart, Richard- 6/19/2002 2:36 PM 34 WASHINGTON UNIVERSITY IN ST LOUIS

SPC II Relative Performance Packet Forwarding Rates in KP/s 25 20 15 KP/s SPC-I/166 10 SPC-II/500 5 SPC-II/700 0 32 CELL (1500 BYTES) PACKETS 15.5 SPC-I/166 23.2 SPC-II/500 23.2 SPC-II/700 Washington DeHart, Richard- 6/19/2002 2:36 PM 35 WASHINGTON UNIVERSITY IN ST LOUIS

SPC II Power Consumption IDLING CURRENT CONSUMPTION 5 4 3 Amps 2 SPC-I/166 SPC-II/500 1 SPC-II/700 0 5V CURRENT 3.3V CURRENT 1 0.8 SPC-I/166 3.4 0.5 SPC-II/500 4.3 0.5 SPC-II/700 Washington DeHart, Richard- 6/19/2002 2:36 PM 36 WASHINGTON UNIVERSITY IN ST LOUIS

SPC II Power Consumption IDLING POWER CONSUMPTION 25 20 15 Watts SPC-I/166 10 SPC-II/500 5 SPC-II/700 0 POWER 7.64 SPC-I/166 18.65 SPC-II/500 23.15 SPC-II/700 Washington DeHart, Richard- 6/19/2002 2:36 PM 37 WASHINGTON UNIVERSITY IN ST LOUIS

Low Power ETX Module Options • 133 MHz AMD Elan (Jumptec) • 266 MHz National Geode (Jumptec) • 266 MHz Mobile Intel Pentium (Jumptec) • 300 MHz Intel Celeron (Jumptec) • 300 MHz National GX1 Geode (Advantech) • 400 MHz Intel Celeron (Advantech) • 400 MHz Intel Celeron (Jumptec) • 400 MHz Intel Pentium III (Jumptec) Washington DeHart, Richard- 6/19/2002 2:36 PM 38 WASHINGTON UNIVERSITY IN ST LOUIS

SPC II Status/Summary • Initial testing has been done on 5 units • 118 SPC-II planars have been fabricated • Lot build-up and testing is underway • FPGA switch VHDL coding is done • FPGA switch place and route is underway • FPGA switch debug yet to do • Delivery to kits groups scheduled for ____. • Each group will get ____. Washington DeHart, Richard- 6/19/2002 2:36 PM 39 WASHINGTON UNIVERSITY IN ST LOUIS