Re-Architecting DRAM Memory Systems with Silicon Photonics Scott - PowerPoint PPT Presentation

Re-Architecting DRAM Memory Systems with Silicon Photonics Scott Beamer 1 , Chen Sun 2 , Yong-jin Kwon 1 , Ajay Joshi 3 , Christopher Batten 4 , Vladimir Stojanovi ć 2 , Krste Asanovi ć 1 1: University of California, Berkeley, CA 2: Massachusetts Institute of Technology, Cambridge, MA 3: Boston University, Boston, MA 4: Cornell University, Ithaca, NY International Symposium on Computer Architecture (ISCA) June 21, 2010

Electrical DRAM is Limited Core Core Compute Chip On-Chip Interconnect Memory Memory Controller Controller On-Chip DRAM Chip Interconnect Page Bank

Electrical DRAM is Limited Core Core Pin-bandwidth on Compute Chip the compute chip On-Chip Interconnect Memory Memory Controller Controller On-Chip DRAM Chip Interconnect Page Bank

Electrical DRAM is Limited Core Core Pin-bandwidth on Compute Chip the compute chip On-Chip Interconnect I/O energy to move between Memory Memory Controller Controller chips On-Chip DRAM Chip Interconnect Page Bank

Electrical DRAM is Limited Core Core Pin-bandwidth on Compute Chip the compute chip On-Chip Interconnect I/O energy to move between Memory Memory Controller Controller chips Cross-chip energy within DRAM chip On-Chip DRAM Chip Interconnect Page Bank

Electrical DRAM is Limited Core Core Pin-bandwidth on Compute Chip the compute chip On-Chip Interconnect I/O energy to move between Memory Memory Controller Controller chips Cross-chip energy within DRAM chip On-Chip DRAM Chip Interconnect Activation energy within DRAM chip Page Bank

Solution: Silicon Photonics Core Core Compute Chip On-Chip Interconnect Memory Memory Controller Controller On-Chip DRAM Chip Interconnect Page Bank

Solution: Silicon Photonics Core Core Great bandwidth Compute Chip density On-Chip Interconnect Great off-chip energy efficiency Memory Memory Controller Controller On-Chip DRAM Chip Interconnect Page Bank

Solution: Silicon Photonics Core Core Great bandwidth Compute Chip density On-Chip Interconnect Great off-chip energy efficiency Memory Memory Controller Controller Costs little additional energy to use on-chip On-Chip DRAM Chip after off-chip Interconnect Page Bank

Solution: Silicon Photonics Core Core Great bandwidth Compute Chip density On-Chip Interconnect Great off-chip energy efficiency Memory Memory Controller Controller Costs little additional energy to use on-chip On-Chip DRAM Chip after off-chip Interconnect Enables page size Page Bank reduction

Outline Technology Background Electrical DRAM Technology Silicon-Photonic Technology Re-Architecting DRAM Memory Systems Chip-Level Bank-Level Evaluation Scaling Capacity with Optical Power Guiding

Current DRAM Structure

Current DRAM Structure Cell wordline bitline

Current DRAM Structure Array Core Cell Cell Row Decoder wordline wordline bitline bitline IO

Current DRAM Structure Array Core Array Block Array Core Helper FFs Cell Cell Cell Row Decoder Row Decoder wordline wordline wordline bitline bitline bitline IO IO Column Decoder

Current DRAM Structure Array Core Array Core Array Block Array Block Array Core Helper FFs Helper FFs Cell Cell Cell Cell Row Decoder Row Decoder Row Decoder wordline wordline wordline wordline bitline bitline bitline bitline IO IO IO Column Decoder Column Decoder I/O Strip Bank Chip

Current DRAM Structure Array Core Array Core Array Core Array Block Array Block Array Block Array Core Helper FFs Helper FFs Helper FFs Cell Cell Cell Cell Cell Row Decoder Row Decoder Row Decoder Row Decoder wordline wordline wordline wordline wordline bitline bitline bitline bitline bitline IO IO IO IO Column Decoder Column Decoder Column Decoder Rank Memory Controller I/O Strip I/O Strip Bank Bank Channel Chip Chip

Photonic Technology Monolithically integrated silicon photonics being researched by MIT Center for Integrated Photonic Systems (CIPS) Backend Poly-Si Dielectric Waveguide STI Silicon Air Gap Substrate Holzwarth et al., CLEO 2008

Photonic Link Die 1 Die 2 Photo- Vertical Ring Ring Off-chip Fiber detector Coupler Modulator Filter Laser Waveguide Each wavelength can transmit at 10Gbps Dense Wave Division Multiplexing (DWDM) 64 wavelengths per direction in same media Rough Comparison Electrical Photonic Off-Chip I/O Energy (pJ/bit) 5 0.150 Off-Chip BW Density (Tbps/mm 2 ) 1.5 50.000

Photonic Summary Power consumers for a photonic link: Light Generation Encode/Decode (Electro-Optical Conversion) Thermal Tuning Features we are leveraging: Better off-chip energy efficiency (bits/J) Better off-chip bandwidth density (b/mm2) Seamless inter-chip links Can be built using mostly standard process

Outline Technology Background Electrical DRAM Technology Silicon-Photonic Technology Re-Architecting DRAM Memory Systems Chip-Level Bank-Level Evaluation Scaling Capacity with Optical Power Guiding

Photonics to the Chip Photonics Off-Chip w/ Electrical Baseline (E1) Electrical On-Chip (P1) E E E E E E E E P P P P P P P P Bank Bank E Electrical Off-Chip Driver P Photonic Data Access Point

Photonics Into the Chip 2 Data Access Points 8 Data Access Points per Column (P2) per Column (P8) Bank Bank Photonic Data Access Point Photonic Data Access Point

Reducing Activate Energy Want to activate less bits while achieving the same access width Increase number of I/Os per array core, which decreases page size Bank Bank DRAM Chip Array Block Activated Row Data Accessed Initial Design Double the I/Os (and bandwidth)

Outline Technology Background Electrical DRAM Technology Silicon-Photonic Technology Re-Architecting DRAM Memory Systems Chip-Level Bank-Level Evaluation Scaling Capacity with Optical Power Guiding

Methodology Photonic Model - aggressive and conservative projections DRAM Model - Heavily modified CACTI-D Custom C++ architectural simulator running random traffic to animate models Setup is configurable, in this presentation: 1 chip to obtain 1GB capacity with >500Gbps of bandwidth provided by 64 banks

Energy for On/Off-Chip Floorplan

Reducing Row Size 4 I/Os per 32 I/Os per Array Core Array Core

Latency Latency marginally better Most of latency is within array core Since array core mostly unchanged, latency only slightly improved by reduced serialization latency

Area 4 I/Os per 32 I/Os per Array Core Array Core

Outline Technology Background Electrical DRAM Technology Silicon-Photonic Technology Re-Architecting DRAM Memory Systems Chip-Level Bank-Level Evaluation Scaling Capacity with Optical Power Guiding

Scaling Capacity Motivation: allow the system to increase capacity without increasing bandwidth

Scaling Capacity Motivation: allow the system to increase capacity without increasing bandwidth Shared Photonic Bus Compute Chip DRAM Chip Laser Vantrease et al., ISCA 2008 Disadvantage : high path loss (grows exponentially) due to couplers and waveguide

Split Photonic Bus Compute Chip DRAM Chip Laser Advantage: much lower path loss Disadvantage: all paths lit

Guided Photonic Bus Compute Chip DRAM Chip Laser Advantage: only 1 low loss path lit

Scaling Results 0.2 P1 Shared 0.15 Laser Energy (pJ/bt) P8 Shared P16 Shared P1 Split 0.1 P8 Split P16 Split P1 Guided 0.05 P8 Guided P16 Guided 0 0 5 10 15 20 25 30 Number of PIDRAM Chips per Channel

With Photonics...

With Photonics... 10x memory bandwidth for same power

With Photonics... 10x memory bandwidth for same power Higher memory capacity without sacrificing bandwidth

With Photonics... 10x memory bandwidth for same power Higher memory capacity without sacrificing bandwidth Area neutral

With Photonics... 10x memory bandwidth for same power Higher memory capacity without sacrificing bandwidth Area neutral Easily adapted to other storage technologies

With Photonics... 10x memory bandwidth for same power Higher memory capacity without sacrificing bandwidth Area neutral Easily adapted to other storage technologies We would like to thank the MIT Center for Integrated Photonic Systems (CIPS) for researching the enabling technology, including: Jason Orcutt, Anatoly Khilo, Benjamin Moss, Charles Holzwarth, Milo š Popovi ć , Hanqing Li, Henry Smith, Judy Hoyt, Franz Kartner, Rajeev Ram, Michael Georgas, Jonathan Leu, John Sun, Cheryl Sorace

With Photonics... 10x memory bandwidth for same power Higher memory capacity without sacrificing bandwidth Area neutral Easily adapted to other storage technologies We would like to thank the MIT Center for Integrated Photonic Systems (CIPS) for researching the enabling technology, including: Jason Orcutt, Anatoly Khilo, Benjamin Moss, Charles Holzwarth, Milo š Popovi ć , Hanqing Li, Henry Smith, Judy Hoyt, Franz Kartner, Rajeev Ram, Michael Georgas, Jonathan Leu, John Sun, Cheryl Sorace This work was in part funded by: