Silicon photonics: a new technology platform to enable a new technology platform to enable low cost and high performance photonics photonics L P L. Pavesi i L. Pavesi 18-11-10
Outline Outline • Silicon Photonics Silicon Photonics • State of the art • Silicon Photonics for lab-on-a-chip Sili Ph t i f l b hi • NanoSilicon photonics • Conclusion L. Pavesi 18-11-10
Outline Outline • Silicon Photonics Silicon Photonics • State of the art • Silicon Photonics for lab-on-a-chip Sili Ph t i f l b hi • NanoSilicon photonics • Conclusion L. Pavesi 18-11-10
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Objective: reduce the cost per single transistor Objective: reduce the cost per single transistor L. Pavesi 18-11-10
29 January 1969 L. Pavesi 18-11-10
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vs Silicon Photonics vs. Silicon Photonics Silicon Photonics LD,PD, microrings, LD,PD, microrings, …. Silicon CMOS L. Pavesi 18-11-10
Silicon photonics Silicon photonics Photonic devices produced within standard silicon factory and with y standard silicon processing L. Pavesi 18-11-10
Silicon pro’s and cons Silicon pro s and cons • Transparent on 1.3-1.5 μ m μ p • CMOS compatibility • Low cost • High index contrast, small footprint • No electro-optic effect • No detection in 1.3-1.5 μ m region • High index contrast coupling • Lacks efficient light emission L. Pavesi 18-11-10
The Opportunity of Silicon Ph Photonics i • Enormous ($ billions) CMOS infrastructure, process Enormous ($ billions) CMOS infrastructure, process learning, and capacity • Draft continued investment in Moore’s law • Potential to integrate multiple optical devices Potential to integrate multiple optical devices • Micromachining could provide smart packaging • Potential to converge computing & communications To benefit from this optical w afers o be e t o t s opt ca a e s m ust run alongside existing product. CMOS PHOTONI CS L. Pavesi 18-11-10
Cost = paradigm change Cost paradigm change • 200 mm Si wafer has 125,000 - 0.5 mm sized dies • Cost processed CMOS wafers $2,000,000 • Cost per die: $16 • Laser size: 10x100 microns. • Cost per laser: $ 0.064 • This is just like estimating the cost of transistors. They are free. Only the PIC cost matters. • Emphasis is moved from components to the system L. Pavesi 18-11-10
Silicon photonics Silicon photonics Basic building blocks L. Pavesi 18-11-10
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Modulator Modulator � Because of its crystal structure, silicon is not a useful conventional electro-optic material useful conventional electro-optic material � Because of its indirect bandgap, silicon has no near bandgap nonlinearities near bandgap nonlinearities � Thermo-optical effect is strong but slow The only effect that is left is the free carrier or Drude effect [ ] 22 18 0 . 8 − − Δ x x . 10 8 . 5 10 ( ) Δ = − 8 Δ + 8 P n N [ [ ] ] 18 18 − − Δ Δ 8 8 . . 5 5 10 10 6 6 . . 0 0 10 10 ( ( ) ) x x x x Δ α Δ α = = Δ Δ + + P P N N R.A. Soref and B.R. Bennett, IEEE JQE 23, 123 (1987) L. Pavesi 18-11-10
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Photodetection Ge Ge Ge Ge Ge Ge Silicon does not absorb IR well Silicon does not absorb IR well Silicon does not absorb IR well Silicon does not absorb IR well • • � Use hybrid approach Use hybrid approach � U � Use SiGe or strained Ge U Use SiGe or strained Ge SiG SiG i i d G d G � Use damaged silicon Use damaged silicon Si Si Si Si L. Pavesi 18-11-10
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Ge photodector Ge photodector IEF-LETI L. Pavesi 18-11-10
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III-V heterogeneous integration for the laser source L. Pavesi 18-11-10
III-V heterointegration for the laser source L. Pavesi 18-11-10
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Where should we integrate the photonics layer ? L. Pavesi 18-11-10
Options 1 Options 1 L. Pavesi 18-11-10
Options 1 Options 1 L. Pavesi 18-11-10
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This requires This requires Spotsize conversion structures Lateral coupling Vertical coupling fiber air φ φ d e r g h x y z • typically based on inverted tapers • typically based on gratings • spotsize: ~3 µm t i 3 • spotsize: ~ 10 µm t i 10 L. Pavesi 18-11-10
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Outline Outline • Silicon Photonics Silicon Photonics • State of the art • Silicon Photonics for lab-on-a-chip Sili Ph t i f l b hi • NanoSilicon photonics • Conclusion L. Pavesi 18-11-10
Explosion of silicon photonics Explosion of silicon photonics L. Pavesi 18-11-10
From Building Block Research From Building Block Research L. Pavesi 18-11-10
To Large scale integration Optical Fiber Multiplexor 25 modulators at 40Gb/ s 25 hybrid lasers 25 hybrid lasers A future integrated 1 Tb/ s optical link A future integrated 1 Tb/ s optical link on a single silicon chip L. Pavesi 46 18-11-10
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Silicon Photonic Link 50Gb 50Gbps Multichip approach Driver 45 nm CMOS Photonic 90 nm CMOS L. Pavesi 18-11-10
Outline Outline • Silicon Photonics Silicon Photonics • State of the art • Silicon Photonics for lab-on-a-chip Sili Ph t i f l b hi • NanoSilicon photonics • Conclusion L. Pavesi 18-11-10
Nanosilicon photonics: a platform where silicon nanoclusters a platform where silicon nanoclusters enable new functionalities in silicon photonics h t i L. Pavesi 18-11-10
Silicon Nanophotonics Silicon Nanophotonics • Confine carriers on nanoscale Confine carriers on nanoscale dimensions • Confine photons on nanoscale dimensions dimensions 10 μ m 10 μ m L. Pavesi 18-11-10
Silicon quantum dots Silicon quantum dots L. Pavesi 50 nm 18-11-10
Silicon quantum dots Silicon quantum dots c-Si c-Si E g E g Nanocrystalline-Si: Bulk Silicon: Direct-gap due to QCE g p Q Indirect band-gap Indirect band gap Strong visible light emission inefficient light emitter L. Pavesi 18-11-10
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Purcel effect Purcel effect L. Pavesi 18-11-10
Integration of microdisk with a waveguide L. Pavesi 18-11-10
pHotonics ELectronics functional Integration on CMOS Integration on CMOS CEIVER RANSC CON TR all SILI THE CMOS capacitor based on Si-NC gate 25/02/2010 59 L. Pavesi Marconi, Anopchenko 18-11-10
pHotonics ELectronics functional Light Emitting Proprieties Light Emitting Proprieties Light Emitting Proprieties Light Emitting Proprieties Integration on CMOS Integration on CMOS CEIVER Forward Bias Reverse Bias RANSC CON TR Poly p-type Luminescent Luminescent all SILI -5 V Region Si substrate n-type Al THE L. Pavesi 18-11-10
pHotonics ELectronics functional Integration on CMOS Integration on CMOS (2 nm SiO 2 / 3 nm SRO) 2 ) 1 1 2 ( μ W / cm Graded energy gap (2 nm SiO 2 / 4 nm SRO) wer density 0.1 0.2 ficiency (%) 0.1 Power eff ptical pow + - 0.01 0.0 n-type -3 -2 -1 1 10 10 10 p-type poly- silicon silicon silicon silicon 2 ) Active Active Current density (mA / cm ) Current density (mA / cm O ∼ 100 wafer Si-NC nm -3 -2 -1 1 1 10 10 10 10 2 ) Current density (mA / cm Current density (mA / cm ) L. Pavesi 18-11-10
pHotonics ELectronics functional Integration on CMOS Integration on CMOS CEIVER Forward Bias Reverse Bias RANSC CON TR Detection R Region i Poly p type Poly p-type all SILI Si substrate n-type Al Al THE 25/02/2010 L. Pavesi 18-11-10
pHotonics ELectronics functional Integration on CMOS Integration on CMOS TTL in TTL in TTL out TTL out 25/02/2010 63 L. Pavesi Marconi 18-11-10
All optical switching with silicon nanocrystals ili t l n=n 0 +n 2 I α = α 0 + β I ( )( ) = − ξ − ξ − Δ ϕ 1 2 1 1 cos T L. Pavesi 18-11-10
Comparison to other nonlinear materials i l Silica n 2 = (1.54x10 -16 ) cm 2 /W [3,4] Bulk Silicon n 2 = (4.5x10 -14 ) cm 2 /W [3,4] GaAs n 2 = (1.59x10 -13 ) cm 2 /W [5] Si-ncs n 2 = (2 ÷ 8x10 -13 ) cm 2 /W [present work] [3] Handbook of Nonlinear Optics [4] Adair R. et al., Physical Review B, 39, 3337, (February 1989). [5] M. Dinu et al., Applied Physics Letters, 82, 2954 (2003). [ ] , pp y , , ( ) L. Pavesi 18-11-10
All optical switching op ca s c g Si nanocrystals activated slot waveguides L. Pavesi A. Martinez et al. Nanoletters (2010) 18-11-10
L. Pavesi A. Martinez et al. Nanoletters (2010) 18-11-10
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