Rapid and Accurate Latch Characterization via Direct Newton - PowerPoint PPT Presentation

Rapid and Accurate Latch Characterization via Direct Newton Solutions of Setup/Hold Times Shweta Srivastava, Jaijeet Roychowdhury Dept of ECE, University of Minnesota, Twin Cities shwetas@umn.edu 1

Outline Current method for finding setup and hold times Motivation and basic idea Contribution: Development of fast characterization method. Problem formulation as a scalar nonlinear algebraic equation. Solving the formulated problem via Newton-Raphson. Results and conclusion 2

Register And Its Behavior output data D Q clock clock setup skew data time Clock-to-Q delay Clock Edge Q: output waveforms Bad, Failed Not desirable Transition time 3

Definition of Setup Time Setup Time: Value of setup skew (delay from data transition edge to clock transition edge) for which clock-to-q delay increases by a certain amount (typically 10%) from the nominal clock-to-q delay. 4

Finding setup time via Bisection method data clock D Q Q Fixed clock hold skew Clock-to-Q delay 10% increase in clock-to-q delay Not to scale Clock -to-q delay Nominal Clock-to-Q delay Setup skew: Setup time Characterization: setup time (not very accurate) Problem Bisection method Large number of transient simulation: Expensive 5

Current Characterization Method: Expensive Characterization of standard cell library takes months . 6

Motivation and Basic Idea Setup and Hold times: prerequisite for timing analysis. Characterization of standard cell library takes months. Need to reduce the characterization time. without losing accuracy . Solution employ Newton-Raphson based solution . A moderate reduction in computation time (i.e less number of transient simulations) can be significant. 7

Contribution Formulate the problem of characterization as a scalar nonlinear algebraic equation A scalar equation with one unknown: setup time Solve the equation via Newton-Raphson method Can hope to converge to solution faster 8

Problem Formulation: Finding Setup Time nominal clock-to-q delay 10% increased clock-to-q delay D Q clk unknown known quantities Q output waveform for different setup skews 9

Selection of Output (Q) Waveform clk clk D Q clk clk D 3 1 2 8 clk clk clk 4 5 6 clk clk Q 7 Positive-edge triggered master-slave register Q output Selection of Q output node Vector of unknown voltages Unit vector 10

Problem Formulation: continued D Q Register equation clk 10% increased clock-to-q delay nominal Q output waveform clock-to-q delay This is the condition we are trying to solve. unknown 11 known quantities

Problem Formulation: continued unknown Q output waveform A scalar nonlinear equation with one unknown. Solution of the equation gives optimal value of tau, i.e. setup time. This 'formulated problem' is very similar to the shooting equation. 12

Solving By Newton Raphson Nonlinear Equation Newton-Raphson evaluate evaluate ? Run transient simulation 13

Computing The Jacobian = Register equation Differentiate w.r.t 14

Computing The Jacobian: continued.. Differentiate above equation w.r.t  Can be solved using any integration method: BE, TRAP etc.. is obtained. 15

Putting It All Together.. Scalar equation that needs to be solved. Start with initial guess evaluate yes converged? Exit No evaluate update 16

Results 17

Results: C 2 MOS master-slave register 4x-6.5x Speedups Positive-edge triggered register Initial guess for setup time was accurate up to 1 digit of accuracy. 18

Results: Transmisson gate based register Positive-edge triggered master-slave register Initial guess of setup time was accurate up to 2 digit of accuracy. ~2.5X Speedups 19

Conclusion Formulation of finding setup/hold times problem as an equation and its solution via Newton-Raphson. Newton-Raphson based method: Speedup: 2.5x-7.5x Can reduce significant amount of time in characterization ? Up to 2 digits of accuracy : Not very useful For 3-7 digits of accuracy: 30 days 11- 3 days Months 11- 4 days Faster design cycle. NR: Good for multivariate unknowns. 20