EE 201: Latchtes and fl ip- fl ops Steven Bell 12 February 2019 By - PowerPoint PPT Presentation

EE 201: Latchtes and fl ip- fl ops Steven Bell 12 February 2019

By the end of class today, you should be able to: Compare and contrast an SR latch , D latch , and D fl ip- fl op Given a circuit containing a latch or fl ip- fl op, draw a timing diagram to illustrate how and when the output changes. Sketch the general strucutre of a sequential circuit Explain why fl ip- fl ops are often preferred over latches for sequential circuit design.

A circuit that counts

S Q NOR This circuit is stable Q R NOR

S Q NOR Q R NOR S S Q Q NOR NOR Q Q R R NOR NOR When S goes high, the output (Q-bar) goes low. This causes the other output (Q) to go high.

S Q NOR Q R NOR S S Q Q NOR NOR Q Q R R NOR NOR S Q Now S goes back low, but Q remains high. NOR Magic! Q R NOR

S Q NOR Now, what happens when R goes high? Q R NOR

S Q NOR Q R NOR S S Q Q NOR NOR Q Q R R NOR NOR When R goes high, Q goes low. And then Q-bar goes high, making things stable again.

S Q NOR Q R NOR S S Q Q NOR NOR Q Q R R NOR NOR S Now when R goes low, the state is Q NOR remembered. Q R NOR

S Q NOR What happens when we start? Q R NOR

S Q NOR Q R NOR S S Q Q NOR NOR Q Q R R NOR NOR

D latch

D fl ip- fl op

The sequential abstraction We use only fl ip- fl ops All fl ip- fl ops are driven by a single clock

Comparison

Practice time http://172.104.217.120:8000/

For Thursday 1. Read the book (4.4-4.5, 5.4) and complete the pre-class quiz 2. Complete the online homework problems and submit via provide