R&D for a monolithic pixel sensor based on 150 nm SOI CMOS technology 11th Vienna Conference on Instrumentation 21 Feb. 2007 T. Tsuboyama (KEK) for the SOIPIX collaboration VCI2007 T. Tsuboyama, 21 Feb. 2007 1
Outline Introduction 2005 designs and preliminary results 2006 designs Effect of radiation and back-gate voltage. Summary VCI2007 T. Tsuboyama, 21 Feb. 2007 2
SOIPIX collaboration KEK: Y. Arai(*), M. Hazumi, Y. Ikegami, T. Kohriki, O. Tajima, S. Terada, T. Tsuboyama, Y. Unno, Y. Ushiroda JAXA: H. Ikeda Niigata Univ.: T. Kawasaki OKI Elec. Ind. Co.: K. Fukuda, H. Hayashi, J. Ida, H. Komatsubara, M. Ohno SLAC: Hiro Tajima Tokyo Institute of Technology: H. Ishino ,Y. Saegusa, T. Takahashi Tsukuba Univ.: K. Hara, H. Miyake, A.Mochizuki Univ. of Hawaii: Gary Varner, Elena Martin (* contact person) VCI2007 T. Tsuboyama, 21 Feb. 2007 3
Pixel sensors Hybrid pixel sensors Hybrid Sensor Proved in LHC experiments. ASIC MEDIPIX: Extended applications to material and biology imaging. bump Monolithic pixel sensor bonding Pixel The radiation detector and readout electronics are integrated in a single wafer. Free from the difficulties in the bump-bonding technology. MAPS Thinning could reduce material significantly. MAPS: Monolithic Active Pixel Sensor Similar to commercial CMOS camera. SUCIMA SOI pixel Epitaxial layer is used as radiation detector. SOI: Silicon on insulator Pioneering work has been done by SUCIMA project. Independent R&D started in 2005 at KEK VCI2007 T. Tsuboyama, 21 Feb. 2007 4
SOI CMOS technology Structure: Low-resistivity silicon layer (for MOSFET) Buried oxide layer (BOX) Gate Silicon substrate (support wafer) MOS FETs are isolated from the MOS substrate and from each other. Low stray capacitance: Faster operation No parasitic transistors: Latch-up free. Insensitive to charge induced in the Si Substrate substrate: Rate of “ single event ” effect is significantly reduced. SOI wafer and process is becoming a standard technology in the semiconductor industry. VCI2007 T. Tsuboyama, 21 Feb. 2007 5
SOI CMOS technology Structure: Low-resistivity silicon layer (for MOSFET) Buried oxide layer (BOX) Gate Silicon substrate (support wafer) MOS FETs are isolated from the MOS substrate and from each other. Low stray capacitance: Faster operation BOX No parasitic transistors: Latch-up free. Insensitive to charge induced in the Si Substrate substrate: Rate of “ single event ” effect is significantly reduced. SOI wafer and process is becoming a standard technology in the semiconductor industry. VCI2007 T. Tsuboyama, 21 Feb. 2007 5
OKI 150 nm SOI CMOS process 0.15 µ m Fully-Depleted SOI CMOS process, Process 1 Poly, 5 Metal layers, MIM capacitor Diameter: 150 mm φ , 3rd metal Top Si : Cz, ~18 Ω -cm, p-type, ~40 nm thick SOI wafer Buried Oxide: 200 nm thick (SOITEC) Handle wafer: Cz>1k Ω -cm, 650 µ m thick 2nd metal Thinned to 350 µ m, plated with Al (200 nm) Backside after the semiconductor process. 1st metal 1 µm Gate Buried oxide MOSFET http:// www.okisemi.com/english/soi.htm Photo of 200-nm SOI VCI2007 T. Tsuboyama, 21 Feb. 2007 6
Substrate contact Sensor structure is made below BOX. Remove the BOX layer where implant is necessary. Inject ions to form p+ or n+ regions. 1st metal Fill back the aperture with SiO 2 . layer Make a via hole. Fill the hole with contact plug. Bias can be applied to substrate and thicker depletion region can be obtained. Plug This procedure is compatible with normal CMOS process. Signal induced in the wafer is Box processed with the CMOS circuit above the BOX. Implant Merits SOI wafer region Thinning can be applied. Standard and up-to-date SOI CMOS technology can be used. VCI2007 T. Tsuboyama, 21 Feb. 2007 7
Substrate contact Sensor structure is made below BOX. Remove the BOX layer where implant is necessary. Inject ions to form p+ or n+ regions. 1st metal Fill back the aperture with SiO 2 . layer Make a via hole. Fill the hole with contact plug. Bias can be applied to substrate and thicker depletion region can be obtained. Plug This procedure is compatible with normal CMOS process. Signal induced in the wafer is Box processed with the CMOS circuit above the BOX. Implant Merits SOI wafer region Thinning can be applied. Standard and up-to-date SOI CMOS technology can be used. VCI2007 T. Tsuboyama, 21 Feb. 2007 7
Substrate contact Sensor structure is made below BOX. Remove the BOX layer where implant is necessary. Inject ions to form p+ or n+ regions. 1st metal Fill back the aperture with SiO 2 . layer Make a via hole. Fill the hole with contact plug. Bias can be applied to substrate and thicker depletion region can be obtained. Plug This procedure is compatible with normal CMOS process. Signal induced in the wafer is Box processed with the CMOS circuit above the BOX. Implant Merits SOI wafer region Thinning can be applied. Standard and up-to-date SOI CMOS technology can be used. VCI2007 T. Tsuboyama, 21 Feb. 2007 7
Substrate contact Sensor structure is made below BOX. Remove the BOX layer where implant is necessary. Inject ions to form p+ or n+ regions. 1st metal Fill back the aperture with SiO 2 . layer Make a via hole. Fill the hole with contact plug. Bias can be applied to substrate and thicker depletion region can be obtained. SiO 2 Plug This procedure is compatible with normal CMOS process. Signal induced in the wafer is Box processed with the CMOS circuit above the BOX. Implant Merits SOI wafer region Thinning can be applied. Standard and up-to-date SOI CMOS technology can be used. VCI2007 T. Tsuboyama, 21 Feb. 2007 7
Substrate contact Sensor structure is made below BOX. Remove the BOX layer where implant is necessary. Inject ions to form p+ or n+ regions. 1st metal Fill back the aperture with SiO 2 . layer Make a via hole. Fill the hole with contact plug. Bias can be applied to substrate and thicker depletion region can be obtained. SiO 2 Plug This procedure is compatible with normal CMOS process. Signal induced in the wafer is Box processed with the CMOS circuit above the BOX. Implant Merits SOI wafer region Thinning can be applied. Standard and up-to-date SOI CMOS technology can be used. VCI2007 T. Tsuboyama, 21 Feb. 2007 7
Substrate contact Sensor structure is made below BOX. Remove the BOX layer where implant is necessary. Inject ions to form p+ or n+ regions. 1st metal Fill back the aperture with SiO 2 . layer Make a via hole. Fill the hole with contact plug. Bias can be applied to substrate and thicker depletion region can be obtained. SiO 2 Plug This procedure is compatible with normal CMOS process. Signal induced in the wafer is Box processed with the CMOS circuit above the BOX. Implant Merits SOI wafer region Thinning can be applied. Standard and up-to-date SOI CMOS technology can be used. VCI2007 T. Tsuboyama, 21 Feb. 2007 7
Substrate contact Sensor structure is made below BOX. Remove the BOX layer where implant is necessary. Inject ions to form p+ or n+ regions. 1st metal Fill back the aperture with SiO 2 . layer Make a via hole. Fill the hole with contact plug. Bias can be applied to substrate and thicker depletion region can be obtained. SiO 2 Plug This procedure is compatible with normal CMOS process. Signal induced in the wafer is Box processed with the CMOS circuit above the BOX. Implant Merits SOI wafer region Thinning can be applied. Standard and up-to-date SOI CMOS technology can be used. VCI2007 T. Tsuboyama, 21 Feb. 2007 7
Substrate contact Sensor structure is made below BOX. Remove the BOX layer where implant is necessary. Inject ions to form p+ or n+ regions. 1st metal Fill back the aperture with SiO 2 . layer SiO 2 Make a via hole. Fill the hole with contact plug. Bias can be applied to substrate and thicker depletion region can be obtained. SiO 2 Plug This procedure is compatible with normal CMOS process. Signal induced in the wafer is Box processed with the CMOS circuit above the BOX. Implant Merits SOI wafer region Thinning can be applied. Standard and up-to-date SOI CMOS technology can be used. VCI2007 T. Tsuboyama, 21 Feb. 2007 7
List of 2005 TEG Name AMPTEG Preamp, Time over threshold, comparator, active feed back etc. RADTEG Pixel, transistor, ring oscillator PIXTEG 32x32 pixel array with readout STRIPTEG Short strip sensor HAWAIITEG Hard X-ray compton polarimeter VCI2007 T. Tsuboyama, 21 Feb. 2007 8
Strip TEG DC coupled strips without active circuit is designed to measure basic characteristics of the sensor part. The 2.5 x 2.5 mm 2 chip is divided into eight regions with different strip width. Breakdown voltage: ~50V. Far less than the expected full depletion voltage (200 V). An infrared camera revealed the breakdown takes place at guard ring. Breakdown voltage could be improved by guard ring design. The charge collection efficiency is not saturated at the breakdown voltage. VCI2007 T. Tsuboyama, 21 Feb. 2007 9
Laser scan Focused IR Laser ( λ =980 Light injection window nm) is injected from the top surface. Beam spot size ~ 10 um. Laser There are windows for light injection. Reasonable charge collection, separation and share between strips are confirmed. When laser spot hits the readout metal traces, the observed charge decreases. VCI2007 T. Tsuboyama, 21 Feb. 2007 10
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