PROCESS STEPS Application Fields Portable Electronics (PC, PDA, - PowerPoint PPT Presentation

PROCESS STEPS

Application Fields • Portable Electronics (PC, PDA, Wireless) • IC Cost (Packaging and Cooling) • Reliability (Electromigration, Latch- up) • Signal Integrity (Switching Noise, DC Voltage Drop) • Thermal Design • Ultra-low-power applications • Space missions (miniaturized satellites) Arun N. Chandorkar, IIT Bombay

Different Constraints for Different Application Fields • Portable devices: Battery life-time • Telecom and military: Reliability (reduced power decreases electromigration, hence increases reliability) • High volume products: Unit cost (reduced power decreases packaging cost) Arun N. Chandorkar, IIT Bombay

Is Transistor a Good Switch? I ≠ 0 I = 0 On I = 1ma/u I = ∞ I ≠ 0 I = 0 Off I ≠ 0 I = 0 Sub-threshold Leakage

MOSFET Scaling Problem: Saturation of IDsat Constant OFF current Limit 5 10 I Dsat (A/m) (drive current) 4 Relaxed OFF current Limit Drive Current (mA/µm) 1.2 Supply Voltage (V) 800 600 NMOS 0.8 400 200 PMOS 0.4 0.25 0.4 0.8 1.0 0.1 0.2 0.3 0.6 Channel Length ( µ m) Source: Intel 0 1 log Id Low Vt 1990 1995 2000 2005  Data from IBM, TI, Intel, AMD, Motorola and High Vt IOFF,low Lucent Vt  Low OFF current desirable IOFF,hig Vg Changhoon Choi, PhD Thesis, Stanford Univ., 2002 h Vt 0

Leakage Power 50% Must stop at 50% 40% Leakage Power (% of Total) 30% 20% 10% 0% 1.5 0.7 0.35 0.18 0.09 0.045 Technology ( µ ) A. Grove, IEDM 2002 Leakage power limits Vt scaling INTEL

The limit is deferent depending on application 100 e) 10 Operation Frequency (a.u.) 1 Subthreshold Leakage (A/ µµ) Source: 2007 ITRS Winter Public Conf.

Gate Oxide is Near Limit 130nm Transistor CoSi2 Si3N4 70 nm Poly Si Gate Electrode 1.5 nm Will high K happen? Gate Oxide Would you count on it? Si Substrate INTEL

Power Increase Microprocessors Trend expected in 2001 Heat generation 2008 (Intel) increase Today: 2002 (Intel) Past: 1972 (Intel) Cause Lg sub-25 nm Lg sub-70 nm Lg 10,000 nm Tr. Number increase Tox 0.7 nm Tox 1.4 nm Tox 1200 nm f 30 GHz Clock Frequency increase f 2.53 GHz f 0.00075 GHz P 10 kW P several 10 W P a few 100 mW N 1.8B N 50 M N 2.25k MIPS 1M MIPS (TIPS) Heat Generation 2002 10W/cm2 Hot Plate Solution: 2006 100W/cm2 Surface of Nuclear Reactor Low supply Voltage 2010 1000W/cm2 Rocket Nozzle 2016 10000W/cm2 Sun Surface P. P. Gelsinger, “Microprocessor for the New Millennium: Challenges, Opportunities, and New Frontiers,” Dig. Tech. 2001 ISSCC, San Francisco, pp.22-23, February, 2001

VT Distribution 0.18 micron 120 ~1000 samples 100 # of Chips 80 ~30mV 60 40 20 0 -39.71 -25.27 -10.83 3.61 18.05 32.49 ∆ VTn(mv) High Freq Low Freq High Freq High Isb Low Isb Medium Isb INTEL

Impact on Path Delays Probability Delay Path Delay Path delay variability due to variations in Vdd, Vt, and Temp Impacts individual circuit performance and power Objective: full chip performance, power, and yield Multivariable optimization of individual circuit—Vdd, Vt, size Optimize each circuit for full chip objectives

Towards the end of the (ITRS) Roadmap • Feature sizes approach single-digit nanometers • Physical and economic limits to scaling Red Brick Wall!  New Technologies – Chemically Assembled Electronic Nanotech. (CAEN) – Extreme Ultraviolet (EUV) Lithography

Qi Xinag, ECS 2004, AMD

Scaling limit ? Channel length? 10 nm Electron Gate Oxd wave length Channel Hiroshi Iwai

5 nm gate length CMOS Is a Real Nano Device!! 5 nm Length of 18 Si atoms H. Wakabayashi et.al, NEC IEDM, 2003 Hiroshi Iwai

Prediction now! Gate length Electron Prediction at present wave length 10 nm Practical limit because of off-leakage between S and D? Tunneling Lg = 5 nm? distance 3 nm MOSFET operation Lg = 2 ~ 1.5 nm? Atom distance 0.3 nm But, no one knows future!

0.8 nm Gate Oxide Thickness MOSFETs operates 0.8 nm: Distance of 3 Si atoms!! By Robert Chau, IWGI 2003

So, we are now in the limitation Of Scaling? Do you believe this or do not????

There is a solution! K: Dielectric Constant To use high-k dielectrics Thick gate high-k dielectrics Thin gate SiO2 Thick Small Almost the same leakage Current electric characteristics However, very difficult and big challenge! Remember MOSFET had not been realized without Si/SiO2!

Choice of High-k elements for oxide Gas or liquid Candidates ● HfO2 based dielectrics are at 1000 K selected as the first Unstable at Si interface ● ● ○ Radio active generation materials, H He because of their merit in Si + MO X M + SiO 2 ① 1) band-offset, ● ● ● ● ● ● Li B ② Si + MO X MSi X + SiO 2 2) dielectric constant B C N O F Ne e 3) thermal stability Si + MO X M + MSi X O Y ③ ① ● ● ● ● ● ● Na Mg Al Si P Al Si P Na S S Cl Ar Cl Ar ② ① ① ① ① ① ① ① ① ① ① ● ● ● ● ② ① ① ① ① ① ① ① ① ① ● ● ● ● K Ca Sc Ti Sc Ti K V V Cr Mn Fc Co Ni Cu Zn Ga Ge As Se Br Kr Cr Mn Fc Co Ni Cu Zn Ga Ge As Se Br Kr ● ● ① ① ① ① ① ① ① ● ① ① ① ① ① ● ① ① ① ① ① ● ● La2O3 based dielectrics Rh Sr Y Zr Nb Mo Tc Ru Rb Pd Ag Cd In Sn Sb Te I Xe are thought to be the next ● ③ ① ① ① ① ① ● ● ● ● ① ① ○ ○ ○ Cs Ba ★ Hf Ta W Re Os generation materials, Ir Pt Au Hg Tl Pb Bi Po At Rn which may not need a ○ ○ ○ ○ ○ ○ ○ ○ thicker interfacial layer Fr Ra ☆ Rf Ha Sg Ns Hs Mt ○ LaCe Pr Nd Pm SmEuGdTbDyHo Er TmY ｂ Lu ★ ★ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ☆ ☆ Ac Th Pa U Np Pu AmCm Bk Cf Es Fm Md No Lr Ac Th Pa U Np Pu AmCm Bk Cf Es Fm Md No Lr R. Hauser, IEDM Short Course, 1999 Hubbard and Schlom, J Mater Res 11 2757 (1996)

Intel’s announcement, January 26, 2007, and IEDM Dec 2010 Hafnium-based high-k material by ALD: EOT= 1nm Specific gate metals ( Intel’s trade secret) Different Metals for NMOS and PMOS Use of 193nm dry lithography From 45 nm to 32 nm Tech. Tr density: 2 times increase Tr witching power: 30% reduction Tr witching speed: 20% improvement S-D leakage power: 5 times reduction Gate oxide leakage: 10 times reduction 45nm processors (Core™2 family processors "Penryn") running Windows* Vista*, Linux* etc. 11nm production in the First half of 2015 or Early 2016.

High-k gate insulator MOSFETs for Intel: EOT=1nm EOT: Equivalent Oxide Thickness PMOS

TIT results EOT = 0.48 nm Transistor with La2O3 Gate Insulator

Conclusion: Technology Progression Bulk CMOS 3D ICs FD SOI CMOS Feature Size raised source/drain halo Wafer bonding Strained Si channel Depletion layer Crystallization Well doping isolation channel Nanowires depletion layer isolation Si buried oxide (tensile) Cu interconnect Si 0.8 Ge 0.2 Optical interconnect Si 1- x Ge x Low- k ILD Si Double-Gate CMOS Metal gate Gate Detectors, lasers, modulators, High k gate dielectric Source Drain waveguides Single e Ge/Si Heterostrcture transistor top-gate channel Ge on Si hetroepitaxy channel back-gate Ge on Insulator isolation buried oxide Molecular device Nanowire B Nanotube + = Spin device Time 2 nm

Carbon Nanotubes

Graphene Device

Graphene Device Electronics(??) • A study of how electrons behave in circuitry made from ultrathin layers of graphite – known as graphene – suggests the material could provide the foundation for a new generation of nanometer scale devices that manipulate electrons as waves – much like photonic systems control light waves.

Graphene 3D structure and Band Diagram

In 2004 two scientists, Andre Geim and Konstantin Novoselov, both of whom would later receive the Nobel Prize for their work In preparation of Graphene

Graphene based (2D Material)Transistor Standard NMOSFET Graphene Based Transistor

Graphene transistor and new possible Ballistic Device

Tunneling Effect

Coulomb Blockade • a Coulomb blockade is the increased resistance at small bias voltage of an electronic device comprising at lease one low-capacitance tunnel junction.

Bottom-Up

Self Assembly • Applicatoins: solar cell, light-emitting diodes, capsule in drug delivery system

Chemical Colloidal Method

Lithography and Etching • Lithography: electron beam, ion beam, nanoimprint, dip pen nanolithography • Etching: wet etching, dry etching, plasma, implantation, photo etching

Split-gate Approach • Use additional voltage to create 2 dimensional confinements to control the shape and size of the quantum dot’s gate. • It’s a combination of e beam lithography, evaporation, lift off, contact annealing

Limitations of CMOS in ~ 10 years • Fundamental physical limit - 8 electron per bit (today 1000 e/bit) • Manufacturing cost - $50 Billion/FAB Moore’s law scaling to an end ??????