Program Interference in MLC NAND Flash Memory: Characterization, - PowerPoint PPT Presentation

Program Interference in MLC NAND Flash Memory: Characterization, Modeling, and Mitigation Yu Cai 1 Onur Mutlu 1 Erich F. Haratsch 2 Ken Mai 1 1 Carnegie Mellon University 2 LSI Corporation

Flash Challenges: Reliability and Endurance P/E cycles § (provided) A few thousand P/E cycles § (required) Writing the full capacity of the drive 10 times per day for 5 years (STEC) > 50k P/E cycles E. Grochowski et al., “Future technology challenges for NAND flash and HDD products”, Flash Memory Summit 2012 2

NAND Flash Memory is Increasingly Noisy Read Write Noisy NAND 3

Future NAND Flash-based Storage Architecture Raw Bit Uncorrectable Memory Error Rate Error BER < 10 -15 Noisy Signal Correction Lower High Processing Our Goals: Model NAND Flash as a digital communication channel Design efficient reliability mechanisms based on the model 4

NAND Flash Channel Model Write Read Noisy NAND (Tx Information) (Rx Information) Simplified NAND Flash channel model based on dominant errors Cell-to-Cell Read Write Additive White Time Variant Interference Gaussian Noise Retention § Neighbor page § Erase operation § Retention program § Program page operation ? Cai et al., “ Flash Correct-and-Refresh: Cai et al., “ Threshold voltage distribution in MLC NAND Retention-aware error management for Flash Memory: Characterization, Analysis, and Modeling ” , increased flash memory lifetime ” , ICCD 2012 DATE 2013 5

Outline n Background on Program Interference n Characterization of Program Interference n Modeling and Predicting Program Interference n Mitigation of Program Interference q Read Reference Voltage Prediction n Conclusions 6

How Current Flash Cells are Programmed n Programming 2-bit MLC NAND flash memory in two steps ER (11) V th 1 0 LSB ER Temp Program (11) (0x) V th 1 0 0 1 MSB ER P2 P1 P3 Program (11) (00) (10) (01) V th 7

Basics of Program Interference (n+1,j-1) (n+1,j) (n+1,j+1) MSB:6 ∆ V xy ∆ V xy ∆ V y WL<2> LSB:3 MSB:4 ∆ V x Victim ∆ V x WL<1> Cell LSB:1 (n,j) MSB:2 ∆ V y ∆ V xy ∆ V xy WL<0> LSB:0 (n-1,j-1) (n-1,j) (n-1,j+1) n Traditional model of victim cell threshold voltage changes when neighbor cells are programmed V ( 2 C V C V 2 C V ) / C Δ = Δ + Δ + Δ victim x x y y xy xy total 8

Previous Work Summary n No previous work experimentally characterized and modeled threshold voltage distributions under program interference n Previous modeling work q Assumes linear correlation between the program interference induced threshold voltage change of the victim cell and the threshold voltage changes of the aggressor cells q Coupling capacitance and total capacitance of each flash cell are the key coefficients of the model, which are process and design dependent random variables q Their exact capacitance values are difficult to determine q Previously proposed model cannot be realistically applied in flash controller 9

Outline n Background on Program Interference n Characterization of Program Interference n Modeling and Predicting Program Interference n Mitigation of Program Interference q Read Reference Voltage Prediction n Conclusions 10

Characterization Hardware Platform Cai et al., “ FPGA-Based Solid-State Drive Prototyping Platform ” , FCCM 2011 11

Characterization Studies n Bitline to bitline program interference n Wordline to wordline program interference q Program in page order q Program out of page order 12

Bitline to Bitline Program Interference Victim Cell P1 State P2 State P3 State Wordline ( N+1 ) Wordline ( N ) L X R Wordline ( N-1 ) L= { P0, P1, P2, P3 } R= { P0, P1, P2, P3 } n V th distributions of victim cells under 16 ( 4 x 4) different neighbor values {L, R} almost overlap n Bitline to bitline program interferences are small 13

WL to WL Interference with In-Page-Order Programming Wordline ( N+1 ) Wordline ( N ) Wordline ( N-1 ) Victim Word-line Program interference increases the threshold voltage of victim cells and causes n threshold voltage distributions shift to the right and become wider Program interference depends on the locations of aggressor cells in a block n Direct neighbor wordline program interference is the dominant source of q interference Neighbor bitline and far-neighbor wordline interference are orders of magnitude q lower 14

WL to WL Interference with Out-of-Page-Order Programming Wordline ( N+1 ) Wordline ( N ) Wordline ( N-1 ) Victim Word-line The amount of program interference depends on the programming order of n pages in a block In-page-order programming likely causes the least amount of interference q Out-of-page-order programming causes much more interference q 15

Comparison under Various Program Interference n Signal-to-noise ratio comparison Out-of-page-order Programming 16

Data Value Dependence of Program Interference MSB ¡Page ¡programmed ¡in ¡aggressor ¡cell 80 Victim ¡<10> Victim ¡<00> Victim ¡<01> 60 Victim ¡Vth ¡Increase 40 20 0 aggressor ¡<11> aggressor<10> aggressor<00> aggressor ¡<01> The amount of program interference depends on the values of both the n aggressor cells and the victim cells 17

Outline n Background on Program Interference n Characterization of Program Interference n Modeling and Predicting Program Interference n Mitigation of Program Interference q Read Reference Voltage Prediction n Conclusions 18

Linear Regression Model n Feature extraction for V th changes based on characterization q Threshold voltage changes on aggressor cell q Original state of victim cell n Enhanced linear regression model j K n M + = before V ( n , j ) ( x , y ) V ( x , y ) V ( n , j ) ∑ ∑ Δ = α Δ + α victim neighbor 0 victim y j K x n 1 = − = + Y = X (vector expression) α + ε n Maximum likelihood estimation of the model coefficients 2 arg min ( X Y ) × α − + λ α 2 1 α 19

Model Coefficient Analysis n Direct above cell dominance n Direct diagonal neighbor second n Far neighbor interference exists n Victim cell ’ s Vth has negative affect 20

Model Accuracy Evaluation (x,y)=(measured before interference, measured after interference) Ideal if no interference With Systematic Deviation (x,y)=(measured before interference, predicted with model) Ideal if prediction is 100% accurate Without Systematic Deviation 21

Distribution of Program Interference Noise n Program interference noise follows multi-modal Gaussian-mixture distribution 22

Program Interference vs P/E Cycles n Program interference noise distribution does not change significantly with P/E cycles 23

Outline n Background on Program Interference n Characterization of Program Interference n Modeling and Predicting Program Interference n Mitigation of Program Interference q Read Reference Voltage Prediction n Conclusions 24

Optimum Read Reference for Flash Memory n Read reference voltage can affect the raw bit error rate g(x) f(x) f(x) g(x) State-A State-B State-A State-B V th V th v 0 v 1 v ref v 0 v ’ ref v 1 v v ' + ∞ + ∞ ref ref BER 2 f ( x ) dx g ( x ) dx BER 1 f ( x ) dx g ( x ) dx = ∫ + ∫ = ∫ + ∫ v v ' − ∞ − ∞ ref ref n There exists an optimal read reference voltage q Predictable if the statistics (i.e. mean, variance) of threshold voltage distributions are characterized and modeled 25

Optimum Read Reference Voltage Prediction n Learning function (periodically, every ~1k P/E cycles) Program known data pattern and test Vth q Program aggressor neighbor cells and test victim Vth after interference q n Optimum read reference voltage prediction q Default read reference voltage + Program interference noise mean

Evaluation Results 30% lifetime improvement Raw bit error rate 32k-bit BCH Code (acceptable BER = 2x10 -3 ) No read reference voltage prediction With read reference voltage prediction n Read reference voltage prediction can reduce raw BER and increase the P/E cycle lifetime

Outline n Background of Program Interference n Program Interference Characterization n Modeling and Predicting Program Interference n Read Reference Voltage Prediction to Mitigate Program Interference n Conclusions 28

Key Findings and Contributions n Methodology: Extensive experimentation with real 2Y-nm MLC NAND Flash chips n Amount of program interference is dependent on q Location of cells (programmed and victim) q Data values of cells (programmed and victim) q Programming order of pages n Our new model can predict the amount of program interference with 96.8% prediction accuracy n Our new read reference voltage prediction technique can improve flash lifetime by 30% 29

Program Interference in MLC NAND Flash Memory: Characterization, Modeling, and Mitigation Yu Cai 1 Onur Mutlu 1 Erich F. Haratsch 2 Ken Mai 1 1 Carnegie Mellon University 2 LSI Corporation