Power Power Efficiency Efficiency of of Wavelength Wavelength- - PowerPoint PPT Presentation

Power Power Efficiency Efficiency of of Wavelength Wavelength- -Routed Routed Optical Optical NoC NoC Topologies Topologies for Global for Global Connectivity of 3D Multi- Connectivity of 3D Multi -Core Processors Core Processors Luca Ramini and Davide Bertozzi PHOTONICA PROJECT PHOTONICA PROJECT UNIVERSITY OF FERRARA (ITALY) UNIVERSITY OF FERRARA (ITALY) Funded by the Italian Government under the Founded “FIRB-Futuro in Ricerca” program in 1391

Optical On-Chip Communication For the first time , the photonic elements necessary to build a complete on-chip Optical Communication Infrastructure such as Modulators, Photodetectors, CMOS Drivers and Receivers are today viable for integration on a silicon chip High-speed High-speed Low-loss waveguides Low-loss waveguides High-efficiency High-efficiency electro-optic electro-optic (<1.7dB/cm ) (<1.7dB/cm ) Broadband routers Broadband routers CMOS compatible Modulators Photodetectors (10 Gb/s- 40 Gb/s) (40 GHz bandwidths, (85fJ/bit - <25fJ/bit) 1A/W responsitivities 1.1 pJ/bit - <50fJ/bit ) Current Roadmap: <1mW/Gb/s/link @ 1 Tbps/link Sources: IBM, Cornell, Columbia Univ. Target Platform for chip-scale optical interconnect technology: 3D stacking of processing, memory and optical layers

Background: Space-Routed ONoCs 3D STACKING APPROACH In order to reserve a communication path between a couple Source – Destination the following steps must be accomplished : 1) Path Setup Request 2) Path Ack 2) Path Ack 3) Data Transmission 4) Teardown � Optical path control (Shacham’07) is expensive (hybrid NoC, path setup latency/contention) � Might not be the most appropriate mechanism for cost - and/or latency-constrained communications (control applications where response time is the key metric , Akesson2011 )

Our focus : Wavelength-Routed ONoCs WAVELENGTH-SELECTIVE ROUTING - Packet routing depends solely on the wavelength of its carrier signal. - Path is configured at design time for a source-destination pair. � It does not depend on ongoing transmissions by other nodes. � No time is spent in Routing/ Arbitration. � Enable Contention-Free Full Connectivity without needing for any path setup/teardown overhead. VIRTUAL VIEW λ1 T1 I1 λ2 λ4 λ4 λ2 Appealing property for T2 λ3 λ3 a Processor-Memory network in mixed λ4 criticality systems T3 (KEY REASON FOR OUR CHOICE) λ1 λ2 T4 I2 CHALLENGES: � HARD TO SCALE TO A LARGE NUMBER OF COMMUNICATION ACTORS � MAINLY PROPOSED IN TERMS OF LOGIC SCHEME SO FAR, OVERLOOKING PHYSICAL IMPLEMENTATION EFFECTS

Key Motivation: Pathfinding On- On -Chip Chip PHASE TRANSITION SISTEM LEVEL DESIGN Sistem Silicon Silicon Communication Communication PROBLEM FROM ELECTRONIC AROUND AN Interconnects Photonic Photonic Architectures Architectures TO OPTICAL NOCS OPTICAL INTERCONNECT Devices Devices Modulators, Bergman et at’07 Receivers, Switching Elements Koohi et at’11 Koohi et at’11 5x5 Switch 5x5 Switch 5x5 Switch 5x5 Switch Matrix on Chip Matrix on Chip OUR WORK IS HERE - Scalability - Scalability to to h hundreds undreds of of Cores Cores - - Cache Cache coherence coherence signaling signaling � � Physical Predictability Physical Predictability - M - Matching atching optical optical NoC NoC parameters to parameters to � � Logic vs. Logic vs. physical physical topology topology system requirements system requirements � � Actual A ctual placement placement - - Interconnect Interconnect & & Memory Memory hierarchy hierarchy constraints constraints codesign codesign � � Utilization Utilization policies policies of of hybrid hybrid interconnects interconnects WE ASSESS THE DEVIATION BETWEEN LOGIC SCHEME AND ITS PHYSICAL IMPLEMENTATION UNDER THE EFFECT OF PLACEMENT CONSTRAINTS TARGETING REAL LIFE SYSTEMS (e.g. 64 cores)

Key Concern:The Predictability Gap This work intends to quantify the Design Predictability Gap of Wavelength-Routed Optical NoCs (WR-ONoCs) under the effect of placement and routing constraints in the target system . I I I I P P I I I I P P 1 1 P P P P 0 0 2 2 3 3 R R R R 0 1 2 3 λ0 λ2 λ1 λ3 λ3 λ1 λ0 λ2 R R R R 8 9 1 1 0 1 I I I I I I P P P P P P 8 8 9 1 1 1 1 1 0 I I I I P P P P 7 6 5 4 R R R R 7 6 5 4 λ7 λ4 λ6 λ5 R R R R 1 λ7 1 λ6 1 λ5 1 λ4 5 4 3 2 I I I I P P P P 1 1 1 1 5 4 3 2 PHYSICAL GAP PHYSICAL GAP INSERTION LOSS? DELAY? POWER? WDM DEGREE? NO. OF NODES? INSERTION LOSS? DELAY? POWER? WDM DEGREE? NO. OF NODES? Physical layer awareness enables to quantify the deviation of the “physical topology” from its “logic connectivity scheme” of the “physical topology” from its “logic connectivity scheme” (not just a matter of efficiency, but even of feasibility!) (not just a matter of efficiency, but even of feasibility!)

Key Contributions: Placement Constraints Topology logic schemes often Topology logic schemes often make unrealistic master and make unrealistic master and slave placement assumptions slave placement assumptions Their actual placement Their actual placement constrains the placement and routing of optical switches and links Key effect this work is going to quantify: The number of waveguide crossings on the actual layout may be much larger than in the logic scheme due to the mapping constraint on a 2D surface THE INSERTION LOSSES and LASER POWER REQUIREMENTS may WORSEN to such an extent that an elegant logic scheme may turn out to be overly expensive and even unfeasible These effects are tightly design-specific, hence urging the choice for an experimental setting : Processor-memory communication in a 3D stacked multi-core processor

Target Architecture: 3D Stacked Multi-core Processor PROMISING SCENARIO PROMISING SCENARIO FOR COST FOR COST– –EFFECTIVE EFFECTIVE INTEGRATION OF INTEGRATION OF HETEROGENEOUS TECHNOLOGIES. HETEROGENEOUS TECHNOLOGIES. SEAMLESS SCALING OF THE OPTICAL LAYER TO DRAM CHIP COMMUNICATION ARRAY OF CONTINUOUS WAVE OFF-CHIP LASERS OPTICAL LAYER IS λ3 λn λ1 λ2 …… VERTICALLY ELECTRONIC STACKED ON TOP LAYER IS LOCATED AT THE BOTTOM TSVs WORK LIKE OF SUCH A A BACKBONE STRUCTURE FOR UPLOADING AND DOWNLOADING INFORMATIONS

Target Architecture: The Electronic Layer The Electronic Layer consists of 64 homogeneous processor cores connected by an Electronic NoC with a 2D Mesh Topology . ASSUMPTIONS E-NoC: 64 cores connected to a 2DMesh PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE � � Cores Cores are grouped into 4 clusters 4 clusters Ci Ci of 16 cores of 16 cores PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE each each each each PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE � � Each cluster PE PE PE PE PE PE PE PE PE PE Each cluster has its own access to the optical its own access to the optical PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE layer layer which is vertically stacked on top of the PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE electronic layer PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE � Core � Core size size is 1mm x 1mm 1mm x 1mm PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE Clusters and Aggregation Factor � � Die Die size size is 8mm x 8mm 8mm x 8mm The number of cores inside each cluster represents the Aggregation Factor Aggregation Factor

Target Architecture: The Optical Layer The Cluster Gateways to the optical layer are defined as the Hubs Hubs (Hi (Hi) ) Wavelength Sharing: the same wavelengths can be shared by all the Initiators. Optical Power: is provided by an array of off-chip Continuous Wave (CW) lasers. CW CW CW CW λ2 λn λ1 ….. λ3 Coupler Coupler Lasers 3 4 H3 H3 M3 M3 H4 H4 M4 M4 1 2 M1 M1 M2 M2 H2 H2 H1 H1 Optical Layer Optical Layer Fiber Ribbon Fiber Ribbon The Optical Layer offers three kinds of communications: (a) Among Clusters (b) From a cluster to a Memory Controller of an off-chip DRAM DIMM (c) From a Memory Controller to a Cluster

PLACEMENT CONSTRAINTS Placement Constraints : The Hubs are positioned in the middle of the clusters λn λ1 λ2 λ3 …… Placement Constraints : The Memory Controllers are positioned pairwise at opposite positions of the chip thus reflecting a conventional industrial practice (e.g. Tilera TILE64)