Pedestal Subtraction - Filtering Kostas Manolopoulos Rutherford - PowerPoint PPT Presentation

Pedestal Subtraction - Filtering Kostas Manolopoulos Rutherford Appleton Laboratory

Trigger Primitive Generation • Trigger Primitive Generation includes pedestal subtraction, filtering and hit-finding of ADC values received from the WIB • Simple algorithms have been implemented & validated Validation is done by converting data captured in playback buffers/testbench to standard DUNE – offline formats and comparing them with sw simulation TPG Output Input Header Stripper Hit Pedestal FIR Finder Subtraction Kostas Manolopoulos (RAL) 2

Pedestal Subtraction Firmware implementation based on Phil’s algorithm for Pedestal Finding • Algorithm: • Start with accumulator=0 and an estimate of the pedestal – If ADCvalue >(<) pedestal => accumulator +(-) 1 – If accumulator = +(-) 10 => pedestal +(-) 1 and reset accumulator to 0 – Implementation completed, 100% agreement between fw & sw • What’s new: State Save/Restore mechanism • Store the pedestal & accumulator value for each channel and retrieve these values when – its time to process a packet from that same channel again. Use of distributed RAM to save BRAM resources – Kostas Manolopoulos (RAL) 3

FIR with State Save/Restore So far we’ve been using a single 32-tap FIR implemented as a Xilinx IP Core • Verified functionality with 100% agreement with sw – What’s new: State Save/Restore mechanism • Store the last 32 data of an incoming packet for each channel – Retrieve the data and preload them into the FIR when it’s time to process a new packet – from that same channel Current approach it to use 2 IP cores and Ping-Pong between them – FIR_0 Input Output FIR_1 RAM Kostas Manolopoulos (RAL) 4

TPG Resource Utilization Resource Utilization Available Utilization % State Save/Restore Implementation • (64 channels) LUT 1321 274080 0.48 Fmax = 250 MHz – LUTRAM 718 144000 0.50 Target device: xczu9eg – FF 3198 548160 0.58 BRAM 1 912 0.11 DSP 32 2520 1.27 Single channel Implementation Resource Utilization Available Utilization % • Fmax = 200 MHz – LUT 958 274080 0.35 Target device: xczu9eg – LUTRAM 448 144000 0.31 FF 1558 548160 0.28 BRAM 0 912 0 DSP 16 2520 0.63 Kostas Manolopoulos (RAL) 5

Next steps Need to fully validate the state save/restore mechanism with large input • of data sets Integrate the new version of the Hit Finding block that will include the • mechanism for switching thresholds between different channels Design a custom FIR filter using the Xilinx DSP primitives • This way we’ll be able to access the DSP registers in order to preload the FIR with the – store state Reduce the number of DSPs back to 32 – Kostas Manolopoulos (RAL) TMTT 6