Outline Basic Input / Output Interrupt hardware architecture - PDF document

Interrupts and Exceptions Outline � Basic Input / Output � Interrupt hardware architecture � Prioritized Interrupts � Interrupt Vectors � Interrupt Handling � Interrupt Service Routines � Interrupt Service Threads � The Shared Data Problem (overhead slides) � Operating systems : Interfacing Interrupt Handling (eCos, Windows Ce) HPI Embedded 2 Operating Systems 1

Motivation � Typical embedded systems react on external events (e.g. closed-loop control) � Predictable response time required � I/O architecture of operating system and application have major influence on responsiveness of real-time system � High reliability required: software faults must be handled, fault recovery – exception handling � Interrupt latency : important real-time performance indication, must be bounded HPI Embedded 3 Operating Systems Input and Output Devices CPU status register device • data registers hold mechanism values that are treated as data by the device data register • status registers provide information about the device operation HPI Embedded 4 Operating Systems 2

Input Output Primitives � CPUs provide programming support for input and output � Special I/O instructions ( in, out ) � Memory-mapped I/O � Addresses for the registers in I/O devices � Normal memory read / write instructions can be used � Example : moving the byte “5” to parallel data register mov dx, 0x03BC mov al, 0x5 out dx, al HPI Embedded 5 Operating Systems Busy-Wait I/O Programming (Polling) // Copying characters from input to output while(true) { // read a character into achar while(read(IN_STATUS)==0); // wait until ready achar = (char) read (IN_DATA); // write achar write(OUT_DATA,achar); write(OUT_STATUS,1); // turn on device while(read(OUT_STATUS)!=0); // wait until done } HPI Embedded 6 Operating Systems 3

Polling vs. Interrupts � Polling � Higher Sampling Frequencies, Higher Accuracy, Typical rates up to 300 kHz � Overhead if no useful data on device � Tradeoff : Precision vs. Utilization � Interrupt � Slower Reaction Times, Typical rates 20 kHz � Less overhead, more efficient – no busy wait, data processed if available � Fire rates must be known/bounded for real-time systems � But longer processing time � Save: Stack Pointer, Program Counter, Context HPI Embedded 7 Operating Systems Input and Output Devices interrupt request status CPU interrupt acknowledge register data / address device • I/O- device asserts the mechanism interrupt request signal when it wants service from data the CPU register • CPU assert interrupt ackn. signal when it is ready to device handle the request HPI Embedded 8 Operating Systems 4

Implementation of Interrupts � CPU checks interrupt request line at the beginning of execution of every instruction � If interrupt has been asserted, CPU will not fetch next instruction pointed by the Program Counter (PC) � CPU saves current PC + some Context � PC will be set to pre-defined interrupt handling routine � Pointer to handler routine at fixed point in memory (vector table), typically 0x00000000 or configurable � Special return instruction (iret) restores PC + saved Context, next “normal” instruction executed HPI Embedded 9 Operating Systems Trigger of Interrupts Level Triggering Edge Triggering HPI Embedded 10 Operating Systems 5

Handling multiple interrupts � Typical system has more that one I/O-device � System must provide more than one interrupt request line � Interrupts and Polling ( check source in case of interrupt ) � Interrupt vectors allow the interrupting device to specify its handler � Interrupt priorities : allow the CPU to recognize some interrupts as more important than others HPI Embedded 11 Operating Systems Prioritized Interrupts interrupt acknowledge log 2 n … device 1 device 2 device n L1 L2 … Ln CPU HPI Embedded 12 Operating Systems 6

Masking � Lower-priority interrupts must be disabled when higher- priority interrupt is handled � If interrupt is acknowledged - CPU stores current priority level into a special register � Some CPUs deactivate interrupts at all � Priorities of subsequent interrupts are checked against the register � When interrupt handler exits, register must be reset � Most architectures define special interrupt return instruction HPI Embedded 13 Operating Systems Interrupt Vectors interrupt vector table head vector 1 handler 1 vector 2 handler 3 vector 3 handler 4 vector device vector 4 handler 2 interrupt interrupt T request :CPU :device acknowledge I M E Interrupt request CPU interrupt acknowledge Interrupt vector HPI Embedded 14 Operating Systems 7

Programmable Interrupt Controller � Shields operating system from electrical details of the interrupt lines � Interrupt priorities can be configured by software � Some PICs provide queues in order to reduce miss rate of interrupts � Modern APIC architecture supports more interrupt lines, faster to program, allows edge-triggered interrupts instead of level-triggered interrupts HPI Embedded 15 Operating Systems Synchronous Interrupts: Exceptions � Synchronous: caused by the execution of an instruction � Caused by a specific (synchronous) machine instruction � trap Motorola 68000, swi Arm, int 80x86 � used to implement system calls � Caused by instructions with error condition � divide by zero � page fault, alignment exception � illegal instructions � Hardware errors HPI Embedded 16 Operating Systems 8

Difference hardware / software interrupt (cont.) � Further interrupts are disabled as soon as an hardware interrupt comes in, but not disabled in the case of a software interrupt � The handler of a software interrupt runs in the context of the interrupting task � The ISR of a hardware interrupt has no connected task context to run in � Some OS provide a separate context for interrupt handlers HPI Embedded 17 Operating Systems Classes of Exceptions Class Cause A/S Return behavior Signal from I/O device Async Always returns to next Interrupt instruction Trap Intentional exception Sync Always returns to next instruction Fault Potentially Sync Might return to current recoverable error instruction Abort Nonrecoverable error Sync Never returns HPI Embedded 18 Operating Systems 9

Interrupts Interrupt: occurs asynchronously as a result of signals from I/O devices that are external to the processor Asynchronous: not caused by the execution of any � particular instruction User Interrupt Example program Control passes to handler handler after current instruction I/O devices: finishes • network adapters Interrupt pin I curr Interrupt goes high handler runs • disk controllers I next during • timer units execution of current • A/D converters instruction Handler returns to next etc. instruction HPI Embedded 19 Operating Systems Traps Trap: intentional exception that occurs as a result of executing an instruction � Synchronous: caused by the execution of an instruction User Trap Example program handler Operating system call: Control passes to handler • read a file Application syscall Trap handler makes a runs I next • terminate a process system call etc. Handler returns to next instruction HPI Embedded 20 Operating Systems 10

Faults Fault: Results from an error condition that a handler might be able to correct Synchronous: caused by the execution of a particular instruction � User Fault Example program handler Page fault exception: Control passes to handler • physical page not in Current I curr Fault handler instruction runs memory causes a fault Handler either reexecutes abort current instruction or aborts HPI Embedded 21 Operating Systems Aborts Abort: results from unrecoverable fatal error, typically hardware errors � Synchronous: caused by the execution of an instruction User Abort Example program handler Hardware errors: Control passes to handler • parity error Fatal hardware I curr Abort handler error occurs runs (DRAM/SRAM bits corrupted) • machine check etc. Handler returns to abort abort routine HPI Embedded 22 Operating Systems 11

Privileged Mode (User-/Kernelmode) � System calls can be performed by generation of a software interrupt (trap) � System calls are handlers of software interrupts ! � Typically system calls copy data to registers or the stack and trigger a software interrupt � For example : Windows NT uses interrupt 2Eh to execute undocumented system calls � MSDOS uses interrupt 21h, BIOS functions accessible via 10h, 13h, 16h (x86) HPI Embedded 23 Operating Systems Interrupt Service Handler Interrupt Service Routines � Should be as short as possible (all other interrupts could be disabled) � Launching of ISRs is not controlled by the operating system, everything is done by the CPU � Typically reading or writing of some registers and buffer them for further reading � Deferred interrupt handling supported by most operating systems HPI Embedded 24 Operating Systems 12