Outline Introduction to CMOS VLSI � Introduction Design � Delay in a Logic Gate � Multistage Logic Networks � Choosing the Best Number of Stages Lecture 5: � Example Logical Effort � Summary David Harris Harvey Mudd College Spring 2004 5: Logical Effort CMOS VLSI Design Slide 2 Introduction Example � � Ben Bitdiddle is the memory designer for the Motoroil 68W86, Chip designers face a bewildering array of choices an embedded automotive processor. Help Ben design the – What is the best circuit topology for a function? ? ? ? decoder for a register file. A[3:0] A[3:0] 32 bits – How many stages of logic give least delay? – How wide should the transistors be? � 4:16 Decoder Decoder specifications: 16 words 16 Register File – 16 word register file � – Each word is 32 bits wide Logical effort is a method to make these decisions – Each bit presents load of 3 unit-sized transistors – Uses a simple model of delay – True and complementary address inputs A[3:0] – Allows back-of-the-envelope calculations – Each input may drive 10 unit-sized transistors – Helps make rapid comparisons between alternatives � Ben needs to decide: – Emphasizes remarkable symmetries – How many stages to use? – How large should each gate be? – How fast can decoder operate? 5: Logical Effort CMOS VLSI Design Slide 3 5: Logical Effort CMOS VLSI Design Slide 4 Delay in a Logic Gate Delay in a Logic Gate � Express delays in process-independent unit � Express delays in process-independent unit d τ = 3RC d = = abs abs d d τ ≈ τ 12 ps in 180 nm process 40 ps in 0.6 µ m process � Delay has two components = + d f p 5: Logical Effort CMOS VLSI Design Slide 5 5: Logical Effort CMOS VLSI Design Slide 6 1
Delay in a Logic Gate Delay in a Logic Gate � Express delays in process-independent unit � Express delays in process-independent unit d d = = d abs d abs τ τ � Delay has two components � Delay has two components = + = + d f p d f p � Effort delay f = gh (a.k.a. stage effort ) � Effort delay f = gh (a.k.a. stage effort) – Again has two components – Again has two components � g : logical effort – Measures relative ability of gate to deliver current – g ≡ 1 for inverter 5: Logical Effort CMOS VLSI Design Slide 7 5: Logical Effort CMOS VLSI Design Slide 8 Delay in a Logic Gate Delay in a Logic Gate � Express delays in process-independent unit � Express delays in process-independent unit d d = = abs abs d d τ τ � Delay has two components � Delay has two components = + = + d f p d f p � Effort delay f = gh (a.k.a. stage effort) � Parasitic delay p – Again has two components – Represents delay of gate driving no load � h : electrical effort = C out / C in – Set by internal parasitic capacitance – Ratio of output to input capacitance – Sometimes called fanout 5: Logical Effort CMOS VLSI Design Slide 9 5: Logical Effort CMOS VLSI Design Slide 10 Delay Plots Delay Plots d = f + p d = f + p 2-input 2-input NAND Inverter NAND Inverter = gh + p 6 = gh + p 6 g = g = 4/3 d d Delay: Delay: 5 p = 5 p = 2 d = d = (4/3)h + 2 � What about g = g = 1 4 4 Normalized Normalized p = p = 1 NOR2? 3 d = 3 d = h + 1 Effort Delay: f 2 2 1 1 Parasitic Delay: p 0 0 0 1 2 3 4 5 0 1 2 3 4 5 Electrical Effort: Electrical Effort: h = C out / C in h = C out / C in 5: Logical Effort CMOS VLSI Design Slide 11 5: Logical Effort CMOS VLSI Design Slide 12 2
Computing Logical Effort Catalog of Gates � DEF: Logical effort is the ratio of the input � Logical effort of common gates capacitance of a gate to the input capacitance of an inverter delivering the same output current . Gate type Number of inputs � Measure from delay vs. fanout plots 1 2 3 4 n � Or estimate by counting transistor widths Inverter 1 2 2 A 4 NAND 4/3 5/3 6/3 (n+2)/3 Y 2 4 B 2 A NOR 5/3 7/3 9/3 (2n+1)/3 A Y Y 1 2 1 1 B Tristate / mux 2 2 2 2 2 C in = 3 C in = 4 C in = 5 XOR, XNOR 4, 4 6, 12, 6 8, 16, 16, 8 g = 3/3 g = 4/3 g = 5/3 5: Logical Effort CMOS VLSI Design Slide 13 5: Logical Effort CMOS VLSI Design Slide 14 Catalog of Gates Example: Ring Oscillator � Parasitic delay of common gates � Estimate the frequency of an N-stage ring oscillator – In multiples of p inv ( ≈ 1) Gate type Number of inputs 1 2 3 4 n Inverter 1 Logical Effort: g = NAND 2 3 4 n Electrical Effort: h = NOR 2 3 4 n Parasitic Delay: p = Tristate / mux 2 4 6 8 2n Stage Delay: d = XOR, XNOR 4 6 8 Frequency: f osc = 5: Logical Effort CMOS VLSI Design Slide 15 5: Logical Effort CMOS VLSI Design Slide 16 Example: Ring Oscillator Example: FO4 Inverter � Estimate the frequency of an N-stage ring oscillator � Estimate the delay of a fanout-of-4 (FO4) inverter d Logical Effort: g = 1 Logical Effort: g = 31 stage ring oscillator in 0.6 µ m process has Electrical Effort: h = 1 Electrical Effort: h = frequency of ~ 200 MHz Parasitic Delay: p = 1 Parasitic Delay: p = Stage Delay: d = 2 Stage Delay: d = Frequency: f osc = 1/(2*N*d) = 1/4N 5: Logical Effort CMOS VLSI Design Slide 17 5: Logical Effort CMOS VLSI Design Slide 18 3
Example: FO4 Inverter Multistage Logic Netw orks � Estimate the delay of a fanout-of-4 (FO4) inverter � Logical effort generalizes to multistage networks = ∏ � Path Logical Effort d G g i C = � Path Electrical Effort out-path H C in-path ∏ ∏ � Path Effort = = Logical Effort: g = 1 F f g h i i i Electrical Effort: h = 4 The FO4 delay is about 200 ps in 0.6 µ m process Parasitic Delay: p = 1 10 x y z 60 ps in a 180 nm process Stage Delay: d = 5 20 g 1 = 1 g 2 = 5/3 g 3 = 4/3 g 4 = 1 f/3 ns in an f µ m process h 1 = x/10 h 2 = y/x h 3 = z/y h 4 = 20/z 5: Logical Effort CMOS VLSI Design Slide 19 5: Logical Effort CMOS VLSI Design Slide 20 Multistage Logic Netw orks Paths that Branch � Logical effort generalizes to multistage networks � No! Consider paths that branch: = ∏ � Path Logical Effort G g 15 i 90 G = C 5 = − � Path Electrical Effort out path H = H C GH = 15 − in path 90 ∏ ∏ � Path Effort = = h 1 = F f g h i i i h 2 = � Can we write F = GH? F = GH? 5: Logical Effort CMOS VLSI Design Slide 21 5: Logical Effort CMOS VLSI Design Slide 22 Paths that Branch Branching Effort � No! Consider paths that branch: � Introduce branching effort – Accounts for branching between stages in path 15 90 + G = 1 C C = on path off path 5 b H = 90 / 5 = 18 C on path GH = 18 15 = ∏ 90 Note: h 1 = (15 +15) / 5 = 6 B b ∏ = i h BH h 2 = 90 / 15 = 6 i � Now we compute the path effort F = g 1 g 2 h 1 h 2 = 36 = 2GH – F = GBH 5: Logical Effort CMOS VLSI Design Slide 23 5: Logical Effort CMOS VLSI Design Slide 24 4
Multistage Delays Designing Fast Circuits = ∑ ∑ = = + � Path Effort Delay D f D d D P F i i F = ∑ � Delay is smallest when each stage bears same effort � Path Parasitic Delay P p i = = 1 ˆ f g h F ∑ N = = + i i D d D P � Path Delay i F � Thus minimum delay of N stage path is = 1 + D NF P N � This is a key result of logical effort – Find fastest possible delay – Doesn’t require calculating gate sizes 5: Logical Effort CMOS VLSI Design Slide 25 5: Logical Effort CMOS VLSI Design Slide 26 Gate Sizes Example: 3-stage path � How wide should the gates be for least delay? � Select gate sizes x and y for least delay from A to B ˆ = = C f gh g x out C in g C y ⇒ = i out C x i in ˆ 45 i f A 8 � Working backward, apply capacitance x y B transformation to find input capacitance of each gate 45 given load it drives. � Check work by verifying input cap spec is met. 5: Logical Effort CMOS VLSI Design Slide 27 5: Logical Effort CMOS VLSI Design Slide 28 Example: 3-stage path Example: 3-stage path x x y y x x 45 45 A 8 A 8 x x y B y B 45 45 Logical Effort G = Logical Effort G = (4/3)*(5/3)*(5/3) = 100/27 Electrical Effort H = Electrical Effort H = 45/8 Branching Effort B = Branching Effort B = 3 * 2 = 6 Path Effort F = Path Effort F = GBH = 125 f = ˆ ˆ = = 3 Best Stage Effort Best Stage Effort f F 5 Parasitic Delay P = Parasitic Delay P = 2 + 3 + 2 = 7 Delay D = Delay D = 3*5 + 7 = 22 = 4.4 FO4 5: Logical Effort CMOS VLSI Design Slide 29 5: Logical Effort CMOS VLSI Design Slide 30 5
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