NAND Flash Memory Laura M. Grupp * , John D. Davis , Steven Swanson - PowerPoint PPT Presentation

The Bleak Future of NAND Flash Memory Laura M. Grupp * , John D. Davis  , Steven Swanson * * Non-volatile Systems Laboratory Department of Computer Science and Engineering University of California, San Diego  Microsoft Research 1

Flash’s Future: Bright Reliability Performance Cost Per Capacity 2

Flash’s Future: Bright Bleak Reliability Performance  Decreasing Write Budget Increasing Density  Cost Per Capacity 3

Flash’s Future: Bright Bleak Reliability Performance  Decreasing Write Budget 8000 7000 Expected Performance Gap Write Latency (µs) 6000 5000 Increasing Density  4000 3000 Cost Per Capacity 2000 1000 0 Low Density Disk Drives Flash 4

Flash’s Future: Bright Bleak Reliability Performance  Decreasing Write Budget 8000 7000 Expected Performance Gap Write Latency (µs) 6000 5000 Increasing Density  4000 What performance & scaling trends can we expect from our SSDs? 3000 Cost Per Capacity 2000 1000 Will the price decline be enough? 0 Low Density Disk Drives High Density Flash Flash 5

Predicting Future Flash-Based SSDs Fixed SSD Architecture Flash Chip Trends Model’s Equations SSD Trends 6

The Constant-Die-Count SSD (SSD-CDC) • Represents High-End ( FusionIO, Virident, OCZ) PCIe Channel 0 Link Flash Flash Flash Flash • Baseline Die 0 Die 1 Die 2 Die 3 – 96 dies Channel 1 – 320 GB Flash Flash Flash Flash Controller Die 0 Die 1 Die 2 Die 3 – 34nm, MLC . . . . . . . . . . . . • Assumptions Channel 23 – Constant die count – Unlimited PCIe Link Flash Flash Flash Flash Die 0 Die 1 Die 2 Die 3 – Channel Speed: 400MB/s 7

The Metrics • Capacity • Latency • Throughput 8

Increasing Density: Multi-bit Cells TLC MLC SLC Multi-Level Cell Triple-Level Cell Single-Level Cell (2 bits) (3 bits) (1 bit) “00” V TH Range V TH Range V TH Range “0” “01” “10” “1” “11” Floating Gate (modifies V TH ) 9

Increasing Density: Moore’s Law 40 ITRS Technology 35 Trend Target 30 25nm-34nm Feature Size (nm) 25 20 6.5nm 15 10 Time 5 0 2009 2014 2019 2024 Year 10

Best Possible Capacity by 2024 16384 TLC-3 4096 43x SSD Capacity (GB) MLC-2 SLC-1 1024 SSD-CDC 256 64 16 100 80 60 40 20 0 11 Feature Size (nm)

The Metrics • Capacity: 43x • Latency • Throughput 12

Collecting Flash Latency Trends • In-house flash testing rig • XUP Virtex-II • Daughter board • 10ns resolution • Chip Collection • 45 chips • 6 companies • 25nm-72nm • SLC, MLC, TLC 13

Empirical Data 3.0 TLC-3 Chip Write Latency (ms) MLC-2 2.0 SLC-1 1.0 0.0 512 128 32 8 Feature Size (nm) 14

Scaling Trends in Empirical Data 3.0 Chip Write Latency (ms) SLC-1 MLC-2 2.0 TLC-3 2x 1.0 2x 0.0 512 128 32 8 Feature Size (nm) 15

Write Latency of SSD-CDC 3.0 SSD-CDC Write Latency (ms) TLC-3 MLC-2 2.0 SLC-1 2.6x 1.0 0.0 16 64 256 1024 4096 16384 16 SSD Capacity (GB)

The Metrics • Capacity: 43x • Latency: 2.6x • Throughput 17

Reduced Bandwidth SSD-CDC Write Bandwidth (MB/s) 3500 SLC-1 3000 MLC-2 2500 TLC-3 2000 1500 0.7x 1000 500 0 Increased Page Size MLC: 4kB, TLC 8kB 16 64 256 1024 4096 16384 18 SSD Capacity (GB)

IOPs – 512B Random Accesses SLC-1 1000 SSD-CDC Write kIOPs MLC-2 800 TLC-3 600 Fastest HDD: 0.2 kIOPs Our Slowest SSD: 32.0 kIOPs 400 0.4x 200 0 16 64 256 1024 4096 16384 SSD Capacity (GB) 19

The Metrics • Capacity: 43x • Latency: 2.6x • Throughput: 0.7x, 0.4x 20

Conclusion • Chip Scaling: A Mixed Bag – Improved: Density and Cost – In Decline: Performance and Reliability • SSDs: Not always a perfect replacement for disks – Do Get: High Capacity & High IOPs – Don’t Get: Low Cost & Low Latency 21

Questions? The Bleak Future of NAND Flash Memory Laura M. Grupp, John D. Davis , Steven Swanson 22

The Model’s Equations Metric Equation 2 𝑪𝒋𝒖𝒕𝑸𝒇𝒔𝑫𝒇𝒎𝒎 𝒒𝒔𝒑𝒌𝒇𝒅𝒖𝒇𝒆 𝑮𝒇𝒃𝒖𝒗𝒔𝒇𝑻𝒋𝒜𝒇 𝒄𝒃𝒕𝒇𝒎𝒋𝒐𝒇 Capacity Capacity Baseline × × 𝑪𝒋𝒖𝒕𝑸𝒇𝒔𝑫𝒇𝒎𝒎 𝒄𝒃𝒕𝒇𝒎𝒋𝒐𝒇 𝑮𝒇𝒃𝒖𝒗𝒔𝒇𝑻𝒋𝒜𝒇 𝒒𝒔𝒑𝒌𝒇𝒅𝒖𝒇𝒆 Latency 𝑫𝒊𝒋𝒒𝑴𝒃𝒖𝒇𝒐𝒅𝒛 + 𝑷𝒘𝒇𝒔𝒊𝒇𝒃𝒆𝑴𝒃𝒖𝒇𝒐𝒅𝒛 𝒆𝒋𝒇𝒕𝑸𝒇𝒔𝑫𝒊𝒃𝒐𝒐𝒇𝒎 − 1 × 𝑸𝒃𝒉𝒇𝑻𝒋𝒜𝒇 Bandwidth 𝑫𝒊𝒃𝒐𝒐𝒇𝒎𝑫𝒑𝒗𝒐𝒖 × , 𝑃𝑞𝑓𝑠𝑏𝑢𝑗𝑝𝑜 ≫ 𝐶𝑣𝑡 𝑇𝑞𝑓𝑓𝑒 𝑫𝒊𝒋𝒒𝑴𝒃𝒖𝒇𝒐𝒅𝒛 𝒆𝒋𝒇𝒕𝑸𝒇𝒔𝑫𝒊𝒃𝒐𝒐𝒇𝒎 − 1 IOPs 𝑫𝒊𝒃𝒐𝒐𝒇𝒎𝑫𝒑𝒗𝒐𝒖 × , 𝑃𝑞𝑓𝑠𝑏𝑢𝑗𝑝𝑜 ≫ 𝐶𝑣𝑡 𝑇𝑞𝑓𝑓𝑒 𝑫𝒊𝒋𝒒𝑴𝒃𝒖𝒇𝒐𝒅𝒛 Measured Value Baseline SSD Design Projected SSD Design 23 Constant SSD Parameter

Lifetime 24

Error Rates 25

Price 26

Read Latency 27

Read Bandwidth 28

Read IOPS – 512B Random Access 29

Scaling Trends in Empirical Data 3.0 Chip Write Latency (ms) SLC-1 MLC-2 2.0 TLC-3 1.0 0.0 508 408 308 208 108 8 Feature Size (nm) 30

Increasing Density: Multi-bit Cells TLC MLC SLC Multi-Level Cell Triple-Level Cell Single Level Cell (3 bits) (2 bits) (1 bit) “00” V TH Range V TH Range V TH Range “0” “01” “10” “1” “11” “MLC - 1” V TH Range “0x” Floating Gate Lower Price (modifies V TH ) Native Number of per Bit “1x” Technology Stored Bits 31